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Data Sheet

AD4684/AD4685

MODES OF OPERATION

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OVERSAMPLING

Oversampling is a common method used in analog electronics

to improve the accuracy of the ADC result. Multiple samples of

the analog input are captured and averaged to reduce the noise

component from quantization noise and thermal noise (kTC) of the

ADC. The AD4684/AD4685 offer a rolling average oversampling

function on chip.

The rolling average oversampling functionality is enabled by writing

a 1 on the OS_MODE bit and a valid nonzero value on OSR,

Bits[2:0], in the CONFIGURATION1 register. Oversampling can be

disabled by writing 0 on the OS_MODE bit and a zero value on

OSR, Bits[2:0] in the CONFIGURATION1 register.

Rolling Average Oversampling

Rolling average oversampling mode can be used in applications

where higher output data rates are required and where higher

SNR or dynamic range is desirable. Rolling average oversampling

involves taking a number of samples, adding the samples together,

and dividing the result by the number of samples taken. This result

is then output from the device. The sample data is not cleared when

the process is completed. The rolling oversampling mode uses a

first in, first out (FIFO) buffer of the most recent samples in the

averaging calculation, allowing the ADC throughput rate and output

data rate to stay the same. Rolling average oversampling mode is

configured by setting the OS_MODE bit to Logic 1 and having a

valid nonzero value in the OSR bits. The oversampling ratio of the

digital filter is controlled using the OSR bits. Table 9 provides the

oversampling bit decoding to select the different oversample rates.

The output result is decimated to 16-bit resolution for the AD4684/

AD4685. If additional resolution is required, this resolution can be

achieved by configuring the RES bit in the CONFIGURATION1

In rolling average oversampling mode, all ADC conversions are

controlled and initiated by the falling edge of CS. When a conver-

sion is complete, the result is loaded into the FIFO. The FIFO

length is eight regardless of the oversampling ratio set. The FIFO is

filled on the first conversion after a power-on reset (POR), the first

conversion after a software controlled hard or soft reset, or the first

conversion after the REFSEL bit is toggled. A new conversion result

is shifted into the FIFO on completion of every ADC conversion,

regardless of the status of the OSR bits and the OS_MODE bit.

This shift allows a seamless transition from no oversampling to roll-

ing average oversampling, or different rolling average oversampling

ratios without waiting for the FIFO to fill.

The number of samples, n, defined by the OSR bits, are taken from

the FIFO, added together, and the result is divided by n. The time

between CS falling edges is the cycle time that can be controlled by

the user, depending on the desired data output rate.

Figure 36 shows the rolling average oversampling mode configura-

tion.

Table 9. Rolling Average Oversampling Overview for the AD4684

Oversampling Ratio

Throughput Rate (kSPS)

SNR (dB Typical)

VREF = 2.5 V

VREF = 3.3 V

RES = 0

RES = 1

RES = 0

RES = 1

Disabled

1000

86.1

88.1

88.2

1000

87.9

88.3

89.4

89.9

1000

90.5

91.3

91.8

92.8

1000

92.8

94.2

93.7

95.6

Figure 36. Rolling Average Oversampling Mode Configuration

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