AD4685 datasheet(23/32 Pages) AD

23 / 32 page

Data Sheet

AD4684/AD4685

INTERFACE

analog.com

Rev. 0 | 23 of 32

The interface to the AD4684/AD4685 is via an SPI. The interface

consists of the CS, SCLK, SDOA, SDOB/ALERT, and SDI pins.

The CS signal frames a serial data transfer and initiates an ADC

conversion process. The falling edge of CS puts the track-and-hold

into hold mode at which point the analog input is sampled and the

bus is taken out of three-state.

The SCLK signal synchronizes data in and out of the device via

the SDOA, SDOB, and SDI signals. A minimum of 16 SCLKs

are required for a write to or read from a register. The minimum

number of SCLK pulses for a conversion read is dependent on the

resolution of the device and the configuration settings.

The ADC conversion operation is driven internally by an on-board

oscillator and is independent of the SCLK signal.

The AD4684/AD4685 have two serial output signals, SDOA and

SDOB. To achieve the highest throughput, use both SDOA and

SDOB, 2-wire mode, to read the conversion results. If a reduced

throughput is required or oversampling is used, it is possible to

use 1-wire mode, SDOA signal only, for reading conversion results.

Programming the SDO bit in the CONFIGURATION2 register con-

figures 2-wire or 1-wire mode.

Configuring a cyclic redundancy check (CRC) operation for SPI

reads, SPI writes, and oversampling modes alters the operation

of the interface. The relevant CRC Read, CRC Write, and CRC

Polynomial sections of this data sheet must be consulted to ensure

correct operation.

READING CONVERSION RESULTS

The CS signal initiates the conversion process. A high to low transi-

tion on the CS signal initiates a simultaneous conversion of both

ADCs, ADC A and ADC B. The AD4684/AD4685 have a one-cycle

readback latency. Therefore, the conversion results are available

on the next SPI access. Then, take the CS signal low, and the

conversion result clocks out on the SDOA and SDOB/ALERT pin.

The next conversion is also initiated at this point. The conversion

result is shifted out of the device as a 16-bit word for the AD4684/

AD4685. The MSB of the conversion result is shifted out on the CS

falling edge. The remaining data is shifted out of the device under

the control of the serial clock (SCLK) input. The data is shifted out

on the rising edge of SCLK, and the data bits are valid on both the

falling edge and the rising edge. After the final SCLK falling edge,

take CS high again to return the SDOA and SDOB/ALERT pins to a

high impedance state.

The number of SCLK cycles to propagate the conversion results on

the SDOA and SDOB/ALERT pins is dependent on the serial mode

of operation configured and if resolution boost is enabled (see

Figure 42 and Table 10 for details). If CRC reading is enabled, addi-

tional SCLK pulses are required to propagate the CRC information

(see the CRC section for more details). As the CS signal initiates a

conversion, as well as framing the data, access must be completed

within a single frame.

Figure 42. Reading Conversion Results

Table 10. Number of SCLKs, n, Required for Reading Conversion Results

Interface Configuration

Resolution Boost Mode

CRC Read

Number of SCLK Pulses

2-Wire

Disabled

Enabled

Disabled

Enabled

1-Wire

Disabled

Enabled

Disabled

Enabled

AD4685 Datasheet(PDF) 23 Page - Analog Devices

AD4685 Datasheet(HTML) 23 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Datasheet Download

Link URL