AD74115H datasheet(52/113 Pages) AD

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Data Sheet

AD74115H

THEORY OF OPERATION

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Rev. 0 | 52 of 113

Sourcing and Sinking Currents up to 100 mA

Internal FETs are available to source or sink up to 100 mA continu-

ous current. A 200 mA start-up current is also accommodated. Us-

ing the internal FETs to provide the digital output current eliminates

the need for external FETs. Push-pull mode uses both the sourcing

and sinking internal FETs. Configure the digital output using the

DO_INT_CONFIG register:

►

Select source, sink, or push-pull capability using the

DO_INT_MODE bits.

►

Select the source of the data for the digital output circuit using

the DO_INT_SRC_SEL bit. The digital output data can be provid-

ed by SPI (via the DO_DATA_INT bit) or by the GPIO_C pin for

faster output rates.

►

Configure the short-circuit timers using the DO_INT_T1 and

DO_INT_T2 bits. See the Short-Circuit Detection section for

more information on short-circuit functionality. Note that T1 short-

circuit limits are not available in push-pull mode.

Once the configuration settings are applied, a new write is required

to the DO_INT_CONFIG register, to set the DO_DATA_INT bit.

Setting the DO_DATA_INT to 1 turns on the selected FET. In

push-pull mode, set the bit to 0 to drive a low on the output and to 1

to drive a high on the output.

For GPIO control, configure the GPIO_x pinto control the digital

output circuit by writing 0x0004 to the GPIO_CONFIGx register.

Drive the GPIO_x pin high to turn on the FET. In push-pull mode,

set the pin low for a low on the output and high for a high on the

output.

If changing from one digital output function to another, first disable

the digital output function before changing to the new mode (set

DO_INT_MODE to digital output internal disable).

The power and isolation companion chip, ADP1034, can provide

the power required to operate the AD74115H in digital output

mode (using the internal FETs) sourcing continuous currents up to

100 mA. The ADP1034 also accommodates the 200 mA start-up

current. In this case, the AVDD pin can be externally connected to

the DO_VDD pin, eliminating the need for an additional DO_VDD

supply source.

Figure 49 shows the current and voltage paths of the digital output

sourcing mode with the internal FET.

Figure 50 shows the current and voltage paths of the digital output

sinking mode with the internal FET.

Figure 49. Digital Output Sourcing Mode with the Internal FET

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