AD74115H datasheet(72/113 Pages) AD

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Data Sheet

AD74115H

APPLICATIONS INFORMATION

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Rev. 0 | 72 of 113

POWER AND ISOLATION

The AD74115H is designed to operate with a companion power and

isolation chip. The ADP1034 provides programmable power control

(PPC) to the analog supply (AVDD) so that VAVDD can be software

controlled. The ADP1034 also provides fixed power supply voltages

to the following AD74115H supply pins: AVSS, AVCC, and DVCC.

The ADP1034 is controlled by the AD74115H via the PPC_CTRL

pin using an OWSI. The host controller issues commands to adjust

the AVDD supply voltage to the PPC_TX register. In turn, the

AD74115H passes the required VAVDD changes to the ADP1034

using the OWSI. Once the ADP1034 receives a command to modify

VAVDD, it updates the VAVDD accordingly.

Choose the PPC_TX register code based on the following equation:

PPC_CODE=252× VÀVDD

VAVDD_MAX

−1

where:

PPC_CODE is the code that must be programmed to the PPC_TX

VAVDD is the desired AVDD supply voltage.

VAVDD_MAXis the maximum voltage that can be generated by

the ADP1034 with the selected feedback resistors. Refer to the

ADP1034 data sheet for more information.

The AVDD supply from the ADP1034 can be dynamically changed

as the load requirement and selected use case changes. Any

changes must be done in a coordinated manner. If the voltage on

the I/OP screw terminal is expected to increase due to a change

in conditions, VAVDD must be adjusted first. If the voltage on the

I/OP screw terminal is expected to decrease due to the change

in conditions, VAVDD must be adjusted after the change in load,

current, or selected use case.

The diagnostics function can confirm that the voltage is set on

the AVDD pin. Select AVDD in one of the available diagnostics in

the DIAG_ASSIGN register. Enable an ADC conversion using the

ADC_CONFIG register and read the diagnostics result using the

relevant ADC_DIAG_RESULTx register.

The ADP1034 provides digital isolation to the AD74115H SPI pins

(SCLK, SYNC, SDO, and SDI). Isolation is available for two other

digital output pins and one digital input pin. The block diagram in

Figure 63 shows that the RESET, ADC_RDY, and ALERT pins are

isolated using the ADP1034.

Refer to the ADP1034 data sheet for more information.

One-Wire Serial Interface

Programmable power control is implemented via an OWSI between

the AD74115H and the ADP1034.

The AD74115H acts as the OWSI main, using the PPC_CTRL pin.

An OWSI transaction requires a number of elements, as shown in

Figure 62. OWSI timing specifications are listed in Table 16. The

OWSI frame is broken into bit periods. Each start event, data bit,

and acknowledge (ACK) bit occurs within a bit period, and each

timing specification is defined from the start of that bit period.

A start sequence is defined by two successive rising edge pulses.

Once the start command is transmitted, 16 data bits follow to make

up the address, data, and CRC bits. Finally, an acknowledge se-

quence is required from the OWSI subordinate. The acknowledge is

comprised of two bits: an ACK bit and a parity bit.

The AD74115H pulls the OWSI bus high at the start of the ACK and

parity bit periods. The OWSI bus is sampled by the AD74115H for

a fixed time during the ACK and parity bits during which the OWSI

subordinate can drive the bus low. Refer to Figure 3 for a detailed

view of the OWSI timing and to Table 16 for the appropriate timing

specifications.

During a successful transaction, the OWSI subordinate remains

high during the ACK bit and drives the bus low during the parity bit.

If the transaction is not successful, the OWSI subordinate drives the

bus low during the ACK bit and remains high during the parity bit.

Figure 62. OWSI Write with Acknowledge

AD74115H Datasheet(PDF) 72 Page - Analog Devices

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