AD74115H datasheet(92/113 Pages) AD

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Data Sheet

AD74115H

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Rev. 0 | 92 of 113

Table 54. Bit Descriptions for GPIO_CONFIG2

Bits

Bit Name

Description

Reset

Access

100: configured to drive internal digital output FET.

101: GPIO_C is configured as an input to control the TXD signal of the HART modem interface. When this mode

is selected on all four GPIO_x pins, the pins can interface with the internal HART modem UART interface. The

internal SPI to UART interface is disabled.

110: GPIO_C is configured to output the TXD signal. All four GPIO_x pins can monitor the HART UART signals.

The GPIO_x input pad buffer is disabled.

111: configured to output the TX_COMPLETE status bit in the HART_ALERT_STATUS register.

GPIO_D Configuration Register

Address: 0x38, Reset: 0x0008, Name: GPIO_CONFIG3

The four GPIO_x registers configure the four GPIO_x pins. A weak pull-down is enabled on each pin, by default, which can be disabled using

the GP_WK_PD_EN bit.

Select the General-Purpose Output

Mode.

General-Purpose Input Data Bit.

Pad Weak Pull-Down Enable

This Bit Sets the GPIO Logic Level

When GPIO_SELECT = 001

[15:6] RESERVED

[2:0] GPIO_SELECT (R/W)

[5] GPI_DATA (R)

[3] GP_WK_PD_EN (R/W)

[4] GPO_DATA (R/W)

Table 55. Bit Descriptions for GPIO_CONFIG3

Bits

Bit Name

Description

Reset

Access

[15:6]

RESERVED

Reserved.

0x0

GPI_DATA

General-Purpose Input Data Bit. This bit reflects the current state of the corresponding pin.

0x0

GPO_DATA

This Bit Sets the GPIO Logic Level When GPIO_SELECT = 001.

0x0

R/W

0: drive a logic low on GPIO_x pin.

1: drive a logic high on GPIO_x pin.

GP_WK_PD_EN

Pad Weak Pull-Down Enable.

0x1

R/W

0: disable weak pull-down.

1: enable weak pull-down.

[2:0]

GPIO_SELECT

Select the General-Purpose Output Mode. Values outside of those listed as follows select the high impedance

option.

0x0

R/W

000: high impedance. The GPIO_x output driver is off. The GPIO_x pad input buffer is disabled.

001: configured as an output. The output level is set by the GPO_DATA bit. The GPIO_x input buffer is disabled.

010: configured as an output and input. The output level is set by the GPO_DATA bit. The GPIO_x input buffer is

enabled so that the output data can also be read via GPI_DATA.

011: configured as an input. GPIO_x output driver is configured in high impedance state.

100: the GPIO_x output driver is off. The GPIO_x pad input buffer is disabled.

101: GPIO_D is configured as an input to control the RTS signal of the HART modem interface. When this mode

is selected on all four GPIO_x pins, the pins can interface with the internal HART modem UART interface. The

internal SPI to UART interface is disabled.

110: GPIO_D is configured to output the RTS signal. All four GPIO_x pins can monitor the HART UART signals.

The GPIO_x input pad buffer is disabled.

111: configured to output the CD status bit in the HART_ALERT_STATUS register.

FET Leakage Compensation Register

Address: 0x39, Reset: 0x0000, Name: FET_LKG_COMP

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