CR14 datasheet(17/46 Pages) STMICROELECTRONICS

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CR14

4 CR14 I²C protocol description

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4.1

I²C Start Condition

START is identified by a High-to-Low transition of the Serial Data line, SDA, while the Serial

Clock, SCL, is stable in the High state. A START condition must precede any data transfer

command.

The CR14 continuously monitors the SDA and SCL lines for a START condition (except during

Radio Frequency data exchanges), and will not respond unless one is sent.

4.2

I²C Stop Condition

STOP is identified by a Low-to-High transition of the Serial Data line, SDA, while the Serial

Clock, SCL, is stable in the High state.

A STOP condition terminates communications between the CR14 and the bus master.

A STOP condition at the end of an I²C Read command, after (and only after) a NoACK, forces

the CR14 into its stand-by state.

A STOP condition at the end of an I²C Write command triggers the Radio Frequency data

exchange between the CR14 and the PICC.

4.3

I²C Acknowledge Bit (ACK)

An acknowledge bit is used to indicate a successful data transfer on the I²C bus.

The bus transmitter, either master or slave, releases the Serial Data line, SDA, after sending 8

bits of data. During the 9th clock pulse the receiver pulls the SDA line Low to acknowledge the

receipt of the 8 data bits.

4.4

I²C Data Input

During data input, the CR14 samples the SDA bus signal on the rising edge of the Serial Clock,

SCL. For correct device operation, the SDA signal must be stable during the Low-to-High Serial

Clock transition, and the data must change only when the SCL line is Low

CR14 Datasheet(PDF) 17 Page - STMicroelectronics