ADC083000 datasheet(5/33 Pages) NSC

5 / 33 page

Pin Descriptions and Equivalent Circuits (Continued)

Pin Functions

Pin No.

Symbol

Equivalent Circuit

Description

CLK+

CLK-

LVDS Clock input pins for the ADC. The differential clock

signal must be a.c. coupled to these pins. The input signal is

sampled on the falling edge of CLK+. See Section 1.1.2 for a

description of acquiring the input and Section 2.3 for an

overview of the clock inputs.

IN+

IN−

Analog signal inputs to the ADC. The differential full-scale

input range is 650 mV

P-P when the FSR pin is low, or 870

P-P when the FSR pin is high.

CMO

Common Mode Voltage. The voltage output at this pin is

required to be the common mode input voltage at V

IN+ and

IN− when d.c. coupling is used. This pin should be grounded

when a.c. coupling is used at the analog inputs. This pin is

capable of sourcing or sinking 100µA. See Section 2.2.

Bandgap output voltage capable of 100 µA source/sink.

126

CalRun

Calibration Running indication. This pin is at a logic high

when calibration is running.

EXT

External bias resistor connection. Nominal value is 3.3k-Ohms

(±0.1%) to ground. See Section 1.1.1.

Tdiode_P

Tdiode_N

Temperature Diode Positive (Anode) and Negative (Cathode)

for die temperature measurements. See Section 2.6.2.

ADC083000 Datasheet(PDF) 5 Page - National Semiconductor (TI)