ADC083000 datasheet(6/33 Pages) NSC

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Pin Descriptions and Equivalent Circuits (Continued)

Pin Functions

Pin No.

Symbol

Equivalent Circuit

Description

36/37

38/39

43/44

45/46

47/48

49/50

54/55

56/57

58/59

60/61

65/66

67/68

69/70

71/72

75/76

77/78

Da0+ / Da0-

Da1+ / Da1-

Da2+ / Da2−

Da3+ / Da3-

Da4+ / Da4−

Da5+ / Da5-

Da6+ / Da6−

Da7+ / Da7-

Dc0+ / Dc0-

Dc1+ / Dc1-

Dc2+ / Dc2−

Dc3+ / Dc3-

Dc4+ / Dc4−

Dc5+ / Dc5-

Dc6+ / Dc6−

Dc7+ / Dc7-

A and C LVDS Data Outputs from the first internal converter.

The data should be extracted in the order ABCD These

outputs should always be terminated with a 100

Ω differential

resistor.

83/84

85/86

89/90

91/92

93/94

95/96

100 / 101

102 / 103

104 / 105

106 / 107

111 / 112

113 / 114

115 / 116

117 / 118

122 / 123

124 / 125

Dd7− / Dd7+

Dd6- / Dd6+

Dd5− / Dd5+

Dd4- / Dd4+

Dd3- / Dd3+

Dd2- / Dd2+

Dd1− / Dd1+

Dd0- / Dd0+

Db7- / Db7+

Db6- / Db6+

Db5− / Db5+

Db4- / Db4+

Db3− / Db3+

Db2- / Db2+

Db1− / Db1+

Db0- / Db0+

B and D LVDS Data Outputs from the second internal

converter. The data should be extracted in the order ABCD

These outputs should always be terminated with a 100

Ω

differential resistor.

OR+

OR-

Out Of Range output. A differential high at these pins

indicates that the differential input is out of range (outside the

range ±325 mV or ±435 mV as defined by the FSR

pin).These outputs should always be terminated with a 100

Ω

differential resistor.

DCLK+

DCLK-

Differential Clock outputs used to latch the output data.

Delayed and non-delayed data outputs are supplied

synchronous to this signal. This signal is at 1/2 the input clock

rate in SDR mode and at 1/4 the input clock rate in the DDR

mode. These outputs should always be terminated with a

100

Ω differential resistor. The DCLK outputs are not active

during the calibration cycle depending on the setting of bit 14

of the RTRIM Disable register (address 9h). DCLK is

continuously present during the calibration cycle when bit 14

is set high and is not active during the calibration cycle when

set low. When the device is in the 1:1 Output Mode, the

signal is at the input clock rate.

ADC083000 Datasheet(PDF) 6 Page - National Semiconductor (TI)

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