ADC083000 datasheet(10/33 Pages) NSC

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Converter Electrical Characteristics (Continued)

NOTE: This product is currently in development and the parameters specified in this section are DESIGN TARGETS.

The specifications in this section cannot be guaranteed until device characterization has taken place. The following

specifications apply after calibration for V

A =VDR = +1.9VDC, OutV = 1.9V, VIN FSR (a.c. coupled) = differential 870mVP-P,CL

= 10 pF, Differential, a.c. coupled Sinewave Input Clock, f

CLK = 1.5GHz at 0.5VP-P with 50% duty cycle, VBG = Floating, Non-

Extended Control Mode, SDR Mode, R

EXT = 3300

Ω ±0.1%, Analog Signal Source Impedance = 100Ω Differential. Boldface

limits apply for T

A =TMIN to TMAX. All other limits TA = 25˚C, unless otherwise noted. (Notes 6, 7)

Symbol

Parameter

Conditions

Typical

(Note 8)

Limits

(Note 8)

Units

(Limits)

ANALOG OUTPUT CHARACTERISTICS

LOAD

CMO

Maximum V

CMO load

Capacitance

Bandgap Reference Output

Voltage

BG = ±100 µA

1.26

1.20

1.33

V (min)

V (max)

TC V

Bandgap Reference Voltage

Temperature Coefficient

A = −40˚C to +85˚C,

BG = ±100 µA

ppm/˚C

LOAD

Maximum Bandgap Reference

load Capacitance

TEMPERATURE DIODE CHARACTERISTICS

∆V

Temperature Diode Voltage

192 µA vs. 12 µA,

J = 25˚C

71.23

192 µA vs. 12 µA,

J = 85˚C

85.54

CLOCK INPUT CHARACTERISTICS

Differential Clock Input Level

Sine Wave Clock

0.6

0.4

2.0

P-P (min)

P-P (max)

Square Wave Clock

0.6

0.4

2.0

P-P (min)

P-P (max)

Input Current

IN =0orVIN =VA

±1µA

Input Capacitance (Notes 10,

11)

Differential

0.02

Each input to ground

1.5

DIGITAL CONTROL PIN CHARACTERISTICS

Logic High Input Voltage

(Note 12)

0.85 x V

V (min)

Logic Low Input Voltage

(Note 12)

0.15 x V

V (max)

Input Capacitance (Notes 11,

13)

Each input to ground

1.2

DIGITAL OUTPUT CHARACTERISTICS

LVDS Differential Output

Voltage

Measured differentially, OutV = V

BG = Floating (Note 15)

710

400

P-P (min)

920

P-P (max)

Measured differentially, OutV =

GND, V

BG = Floating (Note 15)

510

280

P-P (min)

720

P-P (max)

∆ V

O DIFF

Change in LVDS Output Swing

Between Logic Levels

±1mV

Output Offset Voltage, see

Figure 1

BG = Floating

800

Output Offset Voltage, see

Figure 1

BG =VA (Note 15)

1200

∆ V

Output Offset Voltage Change

Between Logic Levels

±1mV

Output Short Circuit Current

Output+ & Output- connected to

0.8V

±4mA

Differential Output Impedance

100

Ohms

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