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ADC083000 Datasheet(PDF) 12 Page - National Semiconductor (TI) |
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ADC083000 Datasheet(HTML) 12 Page - National Semiconductor (TI) |
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12 / 33 page ![]() Converter Electrical Characteristics (Continued) NOTE: This product is currently in development and the parameters specified in this section are DESIGN TARGETS. The specifications in this section cannot be guaranteed until device characterization has taken place. The following specifications apply after calibration for V A =VDR = +1.9VDC, OutV = 1.9V, VIN FSR (a.c. coupled) = differential 870mVP-P,CL = 10 pF, Differential, a.c. coupled Sinewave Input Clock, f CLK = 1.5GHz at 0.5VP-P with 50% duty cycle, VBG = Floating, Non- Extended Control Mode, SDR Mode, R EXT = 3300 Ω ±0.1%, Analog Signal Source Impedance = 100Ω Differential. Boldface limits apply for T A =TMIN to TMAX. All other limits TA = 25˚C, unless otherwise noted. (Notes 6, 7) Symbol Parameter Conditions Typical (Note 8) Limits (Note 8) Units (Limits) AC ELECTRICAL CHARACTERISTICS Pipeline Delay (Latency) (Notes 11, 14) Dd Outputs 13 Input Clock Cycles Db Outputs 14 Dc Outputs 13.5 Da Outputs 14.5 Over Range Recovery Time Differential V IN step from ±1.2V to 0V to get accurate conversion 1 Input Clock Cycle t WU PD low to Rated Accuracy Conversion (Wake-Up Time) 500 ns f SCLK Serial Clock Frequency (Note 11) 100 MHz t SSU Data to Serial Clock Setup Time (Note 11) 2.5 ns (min) t SH Data to Serial Clock Hold Time (Note 11) 1 ns (min) Serial Clock Low Time 4 ns (min) Serial Clock High Time 4 ns (min) t CAL Calibration Cycle Time 1.4 x 10 5 Clock Cycles t CAL_L CAL Pin Low Time See Figure 9 (Note 11) 80 Clock Cycles (min) t CAL_H CAL Pin High Time See Figure 9 (Note 11) 80 Clock Cycles (min) t CalDly Calibration delay determined by pin 127 See Section 1.1.1, Figure 9, (Note 11) 2 25 Clock Cycles (min) t CalDly Calibration delay determined by pin 127 See Section 1.1.1, Figure 9, (Note 11) 2 31 Clock Cycles (max) Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. There is no guarantee of operation at the Absolute Maximum Ratings. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: All voltages are measured with respect to GND = DR GND = 0V, unless otherwise specified. Note 3: When the input voltage at any pin exceeds the power supply limits (that is, less than GND or greater than VA), the current at that pin should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two. This limit is not placed upon the power, ground and digital output pins. Note 4: Human body model is 100 pF capacitor discharged through a 1.5 k Ω resistor. Machine model is 220 pF discharged through ZERO Ohms. Note 5: See AN-450, “Surface Mounting Methods and Their Effect on Product Reliability”. Note 6: The analog inputs are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this device. 20193204 Note 7: To guarantee accuracy, it is required that VA and VDR be well bypassed. Each supply pin must be decoupled with separate bypass capacitors. Additionally, achieving rated performance requires that the backside exposed pad be well grounded. Note 8: Typical figures are at TA = 25˚C, and represent most likely parametric norms. Test limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). www.national.com 12 |
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