NOTE: This product is currently in development and the parameters specified in this section are DESIGN TARGETS.

The specifications in this section cannot be guaranteed until device characterization has taken place. The following

specifications apply after calibration for V

= 10 pF, Differential, a.c. coupled Sinewave Input Clock, f

Extended Control Mode, SDR Mode, R

limits apply for T

Symbol

Parameter

Conditions

Typical

(Note 8)

Limits

(Note 8)

Units

(Limits)

POWER SUPPLY CHARACTERISTICS

I

A

Analog Supply Current

PD = Low

PD = High

745

10.2

TBD

TBD

mA (max)

mA (max)

I

DR

Output Driver Supply Current

PD = Low

PD = High

200

0.012

TBD

TBD

mA (max)

mA (max)

P

D

Power Consumption

PD = Low

PD = High

1.8

20

TBD

TBD

W (max)

mW (max)

PSRR1

D.C. Power Supply Rejection

Ratio

Change in Full Scale Error with

change in V

30

dB

PSRR2

A.C. Power Supply Rejection

Ratio

248 MHz, 50mV

51

dB

AC ELECTRICAL CHARACTERISTICS

f

CLK1

Maximum Input Clock

Frequency

Sampling rate is 2x clock input

1.7

1.5

GHz (min)

f

CLK2

Minimum Input Clock

Frequency

Sampling rate is 2x clock input

500

MHz

Input Clock Duty Cycle

500MHz

≤ Input clock frequency ≤

1.5 GHz (Note 12)

50

20

80

% (min)

% (max)

t

CL

Input Clock Low Time

(Note 11)

333

133

ps (min)

t

CH

Input Clock High Time

(Note 11)

333

133

ps (min)

DCLK Duty Cycle

(Note 11)

50

45

55

% (min)

% (max)

t

RS

Reset Setup Time

(Note 11)

150

ps

t

RH

Reset Hold Time

(Note 11)

250

ps

t

SD

Syncronizing Edge to DCLK

Output Delay

f

f

TBD

TBD

ns

t

RPW

Reset Pulse Width

(Note 11)

4

Clock Cycles

(min)

t

LHT

Differential Low to High

Transition Time

10% to 90%, C

250

ps

t

HLT

Differential High to Low

Transition Time

10% to 90%, C

250

ps

t

OSK

DCLK to Data Output Skew

50% of DCLK transition to 50% of

Data transition, SDR Mode

and DDR Mode, 0˚ DCLK (Note 11)

ps (max)

t

SU

Data to DCLK Set-Up Time

DDR Mode, 90˚ DCLK (Note 11)

667

ps

t

H

DCLK to Data Hold Time

DDR Mode, 90˚ DCLK (Note 11)

667

ps

t

AD

Sampling (Aperture) Delay

Input CLK+ Fall to Acquisition of

Data

1.3

ns

t

AJ

Aperture Jitter

0.4

ps rms

t

OD

Input Clock to Data Output

Delay (in addition to Pipeline

Delay)

50% of Input Clock transition to 50%

of Data transition

3.1

ns

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