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LPC43S50 Datasheet(PDF) 3 Page - NXP Semiconductors |
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LPC43S50 Datasheet(HTML) 3 Page - NXP Semiconductors |
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3 / 156 page  LPC43S50_S30_S20 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2020. All rights reserved. Product data sheet Rev. 1.3 — 20 January 2020 3 of 156 NXP Semiconductors LPC43S50/S30/S20 32-bit ARM Cortex-M4/M0 microcontroller Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMA support. One SPI controller. One Fast-mode Plus I2C-bus interface with monitor mode and with open-drain I/O pins conforming to the full I2C-bus specification. Supports data rates of up to 1 Mbit/s. One standard I2C-bus interface with monitor mode and with standard I/O pins. Two I2S interfaces, each with DMA support and with one input and one output. Digital peripherals External Memory Controller (EMC) supporting external SRAM, ROM, NOR flash, and SDRAM devices. LCD controller with DMA support and a programmable display resolution of up to 1024 H 768 V. Supports monochrome and color STN panels and TFT color panels; supports 1/2/4/8 bpp Color Look-Up Table (CLUT) and 16/24-bit direct pixel mapping. Secure Digital Input Output (SD/MMC) card interface. Eight-channel General-Purpose DMA controller can access all memories on the AHB and all DMA-capable AHB slaves. Up to 164 General-Purpose Input/Output (GPIO) pins with configurable pull-up/pull-down resistors. GPIO registers are located on the AHB for fast access. GPIO ports have DMA support. Up to eight GPIO pins can be selected from all GPIO pins as edge and level sensitive interrupt sources. Two GPIO group interrupt modules enable an interrupt based on a programmable pattern of input states of a group of GPIO pins. Four general-purpose timer/counters with capture and match capabilities. One motor control Pulse Width Modulator (PWM) for three-phase motor control. One Quadrature Encoder Interface (QEI). Repetitive Interrupt timer (RI timer). Windowed watchdog timer (WWDT). Ultra-low power Real-Time Clock (RTC) on separate power domain with 256 bytes of battery powered backup registers. Alarm timer; can be battery powered. Analog peripherals One 10-bit DAC with DMA support and a data conversion rate of 400 kSamples/s. Two 10-bit ADCs with DMA support and a data conversion rate of 400 kSamples/s. Up to eight input channels per ADC. Unique ID for each device. Power Single 3.3 V (2.2 V to 3.6 V) power supply with on-chip internal voltage regulator for the core supply and the RTC power domain. RTC power domain can be powered separately by a 3 V battery supply. Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down. Processor wake-up from Sleep mode via wake-up interrupts from various peripherals. |
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