ADS1285 datasheet(39/67 Pages) TI

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Be aware the corner frequency programming is a function of fDATA. As shown by Equation 5, the value written to

the HPF1, HPF0 registers is value a, computed by Equation 4, × 216.

HPF[15:0] = a × 216

(5)

Table 8-6 shows examples of the high-pass filter programming.

Table 8-6. High-Pass Filter Value Examples

HPF[15:0]

fC (Hz)

fDATA (SPS)

0332h

0.5

250

0332h

1.0

500

019Ah

1.0

1000

The HPF accumulates data to perform the high-pass function. Similar to the operation of an analog HPF after a

dc step change is applied to the input, the filter takes time to accumulate data to remove dc from the signal. The

lower the corner frequency, the longer the filter takes to settle.

To shorten the HPF settling time, the offset register is used as a seed value for the HPF accumulator. The

accumulator is loaded with the offset register each time the HPF state is changed from disabled to enabled. The

offset register can be preset with an estimated value, or a calibrated value if the dc level is known. To improve

accuracy, scale the offset value by the inverse value of GAIN[3:0] / 400000h. The normal offset operation is

disabled when the HPF is enabled.

To initialize the HPF accumulator with the OFFSET[2:0] registers:

1. Disable the HPF.

2. Write the desired value to the OFFSET[2:0] registers.

3. Enable the HPF. OFFSET[2:0] is loaded to the HPF data accumulator.

4. The HPF tracks the remaining dc value from the signal.

Subsequent writes to the OFFSET[2:0] registers are ignored. To reload the contents of the OFFSET[2:0]

registers to the HPF, disable and re-enable the HPF.

8.3.7 Clock Input

A clock signal is required for operation. The clock signal is applied to the CLK pin at fCLK = 8.192 MHz for high-

and mid-power modes and 4.096 MHz for low-power mode. As with many precision data converters, a low-jitter

clock is required to achieve data sheet performance. Avoid the use of R-C clock oscillators. A crystal-based

clock source is recommended. Avoid ringing on the clock signal by placing a series resistor in the clock PCB

trace to source-terminate. Keep the clock signal routed away from other clock signals, input pins, and analog

components.

8.3.8 GPIO

The ADC provides two general-purpose I/O (GPIO) pins that can be used as digital inputs or outputs. The GPIO

voltage levels are IOVDD and DGND. Figure 8-19 illustrates the GPIO block diagram.

The GPIOs are programmed by the GPIO register. The GPIOs are programmed as an input or output by the

GPIOx_DIR bits. The GPIO state is read or written by the GPIOx_DAT bits. When programmed as an output,

reading the GPIOx_DAT bits returns the register bit value previously written. If the GPIOs are unused, terminate

the GPIOs with pulldown resistors to prevent the pins from floating.

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ADS1285

SBAS559A – MAY 2022 – REVISED DECEMBER 2022

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