ADS1285 datasheet(42/67 Pages) TI

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Because the SRC is a digital function, operation is deterministic without error. The SRC trim value can be written

all at the same time, or written incrementally up to a target value to minimize the step change of frequency.

Use the multibyte command operation to write to the SRC registers and complete the write operation 256 CLK

cycles before the DRDY falling edge. This procedure loads the high and low bytes simultaneously before they

are internally processed. See Figure 6-7 for details.

8.4.6 Offset and Gain Calibration

The ADC integrates calibration registers to correct offset and gain errors. As shown in Equation 6 and Figure

8-20, the 24-bit offset value (OFFSET[23:0]) is subtracted from the filter data before multiplication by the 24-bit

gain value (GAIN[23:0]), divided by 400000h. The data are clipped to 32 bits to yield the final output. The offset

operation is bypassed when the high-pass filter is enabled.

Output =

GAIN[23:0]

(Input - OFFSET[23:0])

400000h

(6)

OFFSET[23:0]

GAIN[23:0]

output data

clipped to 32 bits

final output

400000h

offset bypassed in HPF mode

from digital filter

Figure 8-20. Calibration Block Diagram

8.4.6.1 OFFSET Register

Offset correction is by a 24-bit word consisting of three 8-bit registers (high address is the MSB). The offset

value is left-justified to align to the 32-bit data. The offset value is 2's-complement coding with a maximum

positive value of 7FFFFFh and a maximum negative value of 800000h. OFFSET is subtracted from the

conversion data; see Table 8-8. Offset error is corrected by the offset calibration command with the input-short

multiplexer option, or by collecting shorted-input ADC data and writing the value to the registers.

Although the offset correction range is from –FS to +FS, the sum of offset and gain correction must not exceed

106% of the uncalibrated range.

When the high-pass filter is enabled, offset correction is disabled. The offset value is used instead as a starting

value to shorten the high-pass filter settling time. To reload the offset value to the HPF, disable and re-enable the

high-pass filter. See the HPF Stage section for more details.

Table 8-8. Offset Calibration Values

OFFSET[31:0]

CALIBRATED OUTPUT CODE (1)

00007Fh

FFFF8100h

000000h

00000000h

FFFF7Fh

00008100h

(1)

Ideal code value with no offset error.

8.4.6.2 GAIN Register

Gain correction is through a 24-bit word, consisting of three 8-bit registers (high address = MSB). The gain value

is 24 bits, coded in straight binary and normalized to 1.0 for GAIN[23:0] equal to 400000h. With a calibration

signal applied, gain error is calibrated by either the gain calibration command, or by collecting ADC data and

writing a computed value to the gain registers. Table 8-9 lists examples of the GAIN[23:0] register values.

Although the range of gain values can be much greater or less than 1, the sum of offset and gain correction must

not exceed 106% of the uncalibrated range.

ADS1285

SBAS559A – MAY 2022 – REVISED DECEMBER 2022

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