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DP83848-HT

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SLLSEJ7 – FEBRUARY 2015

Table 47. PHY Status Register (PHYSTS), Address 0x10 (continued)

BIT

BIT NAME

DEFAULT

DESCRIPTION

Duplex:

This bit indicates duplex status and is determined from Auto-

Negotiation or Forced Modes.

1 = Full duplex mode

Duplex Status

0, RO

0 = Half duplex mode

Note: This bit is only valid if Auto-Negotiation is enabled and complete

and there is a valid link or if Auto-Negotiation is disabled and there is

a valid link.

Speed10:

This bit indicates the status of the speed and is determined from Auto-

Negotiation or Forced Modes.

1 = 10 Mb/s mode

Speed Status

0, RO

0 = 100 Mb/s mode

Note: This bit is only valid if Auto-Negotiation is enabled and complete

and there is a valid link or if Auto-Negotiation is disabled and there is

a valid link.

Link Status:

This bit is a duplicate of the Link Status bit in the BMSR register,

except that it will not be cleared upon a read of the PHYSTS register.

Link Status

0, RO

1 = Valid link established (for either 10 or 100 Mb/s operation)

0 = Link not established

8.6.3.2 MII Interrupt Control Register (MICR)

This register implements the MII interrupt PHY specific control register. Sources for interrupt generation include:

energy detect state change, link state change, speed status change, duplex status change, auto-negotiation

complete or any of the counters becoming half-full. The individual interrupt events must be enabled by setting

bits in the MII interrupt status and event control register (MISR).

Table 48. MII Interrupt Control Register (MICR), Address 0x11

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:3

RESERVED

0, RO

Reserved: Write ignored, Read as 0

Test Interrupt:

Forces the PHY to generate an interrupt to facilitate interrupt testing.

Interrupts will continue to be generated as long as this bit remains set.

TINT

0, RW

1 = Generate an interrupt

0 = Do not generate interrupt

Interrupt Enable:

Enable interrupt dependent on the event enables in the MISR register.

INTEN

0, RW

1 = Enable event based interrupts

0 = Disable event based interrupts

Interrupt Output Enable:

Enable interrupt events to signal via the PWR_DOWN/INT pin by

configuring the PWR_DOWN/INT pin as an output.

INT_OE

0, RW

1 = PWR_DOWN/INT is an Interrupt Output

0 = PWR_DOWN/INT is a Power Down Input

8.6.3.3 MII Interrupt Status and Miscellaneous Control Register (MISR)

This register contains event status and enables for the interrupt function. If an event has occurred since the last

read of this register, the corresponding status bit will be set. If the corresponding enable bit in the register is set,

an interrupt will be generated if the event occurs. The MICR register controls must also be set to allow interrupts.

The status indications in this register will be set even if the interrupt is not enabled.

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