DP83848-HT datasheet(59/81 Pages) TI

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DP83848-HT

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SLLSEJ7 – FEBRUARY 2015

8.6.3.5 Receiver Error Counter Register (RECR)

This counter provides information required to implement the “Symbol Error During Carrier” attribute within the

PHY managed object class of Clause 30 of the IEEE 802.3u specification.

Table 51. Receiver Error Counter Register (RECR), Address 0x15

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:8

RESERVED

0, RO

RESERVED: Writes ignored, Read as 0

RX_ER Counter:

When a valid carrier is present and there is at least one occurrence of

an invalid data symbol, this 8-bit counter increments for each receive

7:0

RXERCNT[7:0]

0, RO/COR

error detected. This event can increment only once per valid carrier

event. If a collision is present, the attribute will not increment. The

counter sticks when it reaches its max count.

8.6.3.6 100 Mb/s PCS Configuration and Status Register (PCSR)

This register contains event status and enables for the interrupt function. If an event has occurred since the last

read of this register, the corresponding status bit will be set. If the corresponding enable bit in the register is set,

an interrupt will be generated if the event occurs. The MICR register controls must also be set to allow interrupts.

The status indications in this register will be set even if the interrupt is not enabled.

Table 52. 100 Mb/s PCS Configuration and Status Register (PCSR), Address 0x16

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:13

RESERVED

<00>, RO

RESERVED: Writes ignored, Read as 0

RESERVED

RESERVED: Must be zero

RESERVED

RESERVED: Must be zero

100Mbs True Quiet Mode Enable:

TQ_EN

0, RW

1 = Transmit True Quiet Mode

0 = Normal Transmit Mode

Signal Detect Force PMA:

SD FORCE PMA

0, RW

1 = Forces Signal Detection in PMA

0 = Normal SD operation

Signal Detect Option:

SD_OPTION

1, RW

1 = Enhanced signal detect algorithm

0 = Reduced signal detect algorithm

Descrambler Timeout:

Increase the descrambler timeout. When set this should allow the

device to receive larger packets (>9k bytes) without loss of

DESC_TIME

0, RW

synchronization.

1 = 2 ms

0 = 722 µs (per ANSI X3.263: 1995 (TP-PMD) 7.2.3.3e)

RESERVED

RESERVED: Must be zero

Force 100Mb/s Good Link:

FORCE_100_OK

0, RW

1 = Forces 100Mb/s Good Link

0 = Normal 100Mb/s operation

RESERVED

RESERVED: Must be zero

RESERVED

RESERVED: Must be zero

NRZI Bypass Enable:

NRZI_BYPASS

0, RW

1 = NRZI Bypass Enabled

0 = NRZI Bypass Disabled

RESERVED

RESERVED: Must be zero

RESERVED

RESERVED: Must be zero

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