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DP83848-HT Datasheet(PDF) 16 Page - Texas Instruments |
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DP83848-HT Datasheet(HTML) 16 Page - Texas Instruments |
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16 / 81 page  TX_CLK TX_EN PWD output pair PMD output pair 0 0 T2.16.1 T2.16.2 1 1 TX_CLK TX_EN TXD PMD output pair T2.15.2 T2.15.1 DP83848-HT SLLSEJ7 – FEBRUARY 2015 www.ti.com Table 15. 10BASE-T Transmit Timing (Start of Packet) PARAMETER NOTES MIN TYP MAX UNIT T2.15.1 Transmit output delay from the falling edge of 10 Mb/s MII mode 3.5 bits TX_CLK T2.15.2 Transmit output delay from the rising edge of 10 Mb/s Serial mode 3.5 bits TX_CLK Figure 15. 10BASE-T Transmit Timing (Start of Packet) Table 16. 10BASE-T Transmit Timing (End of Packet) PARAMETER NOTES MIN TYP MAX UNIT T2.16.1 End of packet high time (with ‘0’ ending bit) 300 ns T2.16.2 End of packet high time (with ‘1’ ending bit) 300 ns Figure 16. 10BASE-T Transmit Timing (End of Packet) 16 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: DP83848-HT |
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