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DP83848-HT Datasheet(PDF) 19 Page - Texas Instruments |
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DP83848-HT Datasheet(HTML) 19 Page - Texas Instruments |
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19 / 81 page  SD+ internal PMD Input Pair T2.23.1 T2.23.2 Fast link pulses T2.22.1 T2.22.3 T2.22.2 T2.22.1 T2.22.5 T2.22.4 clock pulse clock pulse data pulse FLP burst FLP burst DP83848-HT www.ti.com SLLSEJ7 – FEBRUARY 2015 Table 22. Auto-Negotiation Fast Link Pulse (FLP) Timing (continued) PARAMETER NOTES MIN TYP MAX UNIT T2.22.3 Clock pulse to data pulse period Data = 1 62 μs T2.22.4 Burst width 2 ms T2.22.5 FLP burst to FLP burst period 16 ms Figure 22. Auto-Negotiation Fast Link Pulse (FLP) Timing Table 23. 100BASE-TX Signal Detect Timing PARAMETER NOTES(1) MIN TYP MAX UNIT T2.23.1 SD internal turn-on time 1 ms T2.23.2 SD internal turn-off time 350 µs (1) The signal amplitude on PMD Input Pair must be TP-PMD compliant. Figure 23. 100BASE-TX Signal Detect Timing Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 19 Product Folder Links: DP83848-HT |
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