DP83848-HT datasheet(23/81 Pages) TI

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CRS_DV

RXD[1:0]

RX_ER

T2.27.2

T2.27.1

T2.27.2

PMD Input Pair

T2.27.3

T2.27.5

RX_DV

T2.27.2

IDLE

(J/K)

Data

(TR)

Data

T2.27.4

DP83848-HT

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SLLSEJ7 – FEBRUARY 2015

Table 27. RMII Receive Timing

PARAMETER

NOTES(1)(2)(3)

MIN

TYP

MAX

UNIT

T2.27.1

X1 clock period

50 MHz Reference Clock

T2.27.2

RXD[1:0], CRS_DV, RX_DV and

RX_ER output delay from X1 rising

T2.27.3

CRS ON delay

From JK symbol on PMD receive pair

18.5

bits

to initial assertion of CRS_DV

T2.27.4

CRS OFF delay

From TR symbol on PMD receive

bits

pair to initial deassertion of CRS_DV

T2.27.5

RXD[1:0] and RX_ER latency

From symbol on receive pair.

bits

Elasticity buffer set to default value

(01).

(1)

Per the RMII Specification, output delays assume a 25-pF load.

(2)

CRS_DV is asserted asynchronously in order to minimize latency of control signals through the why. CRS_DV may toggle

synchronously at the end of the packet to indicate CRS deassertion.

(3)

RX_DV is synchronous to X1. While not part of the RMII specification, this signal is provided to simplify recovery of receive data.

Figure 27. RMII Receive Timing

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