AP63200Q/AP63201Q/AP63203Q/AP63205Q

Document number: DS43698 Rev. 1 - 2

27 of 30

www.diodes.com

September 2021

© Diodes Incorporated

AP63200Q/AP63201Q/AP63203Q/AP63205Q

Layout

PCB Layout

1.

The AP63200Q/AP63201Q/AP63203Q/AP63205Q works at 2A load current so heat dissipation is a major concern in the layout of the PCB.

2oz copper for both the top and bottom layers is recommended.

2.

Place the input capacitors as closely across VIN and GND as possible.

3.

Place the inductor as close to SW as possible.

4.

Place the output capacitors as close to GND as possible.

5.

Place the feedback components as close to FB as possible, if applicable. If using AP63203Q/AP63205Q, tie the FB pin directly to VOUT as

there is no need for R1, R2, or C4.

6.

If using four or more layers, use at least the 2nd and 3rd layers as GND to maximize thermal performance.

7.

Add as many vias as possible around both the GND pin and under the GND plane for heat dissipation to all the GND layers.

8.

Add as many vias as possible around both the VIN pin and under the VIN plane for heat dissipation to all the VIN layers.

9.

See Figure 77 for more details.

FB

EN

VIN

GND

SW

BST

C1

C2

R2

L

C3

GND

SW

VOUT

VIN

FB

Figure 77. Recommended PCB Layout