LCS705LG datasheet(16/30 Pages) POWERINT

16 / 30 page

Rev. G 05/17

LCS700-708

www.power.com

It should be noted that the 4.7 nF decoupling capacitor, C

FB (see Figure

19), in conjunction with the 2.5 kΩ input resistance presented by the

FEEDBACK pin, form a pole in the LLC transfer function. This can add

significant phase lag to the feedback loop. A typical value for a 250 kHz

design with a 3 kHz crossover frequency is 4.7 nF. To prevent loop

instability, the value of the 4.7 nF capacitor should not be increased

arbitrarily. At the other extreme, insufficient FEEDBACK pin bypass

capacitance or poor layout may cause duty cycle asymmetry.

Start-Up and Auto-Restart

At start-up and during the off-state of the auto-restart cycle, the

FEEDBACK pin is internally pulled up to the VREF pin. This keeps the

output MOSFETs off and discharges the soft-start capacitor, in

preparation for soft-start.

At start-up, this state remains for 1024 clock cycles at frequency f

MAX.

During the off-state of auto-restart, or if the OV/UV or IS pin is

triggered while the VCC remains above its UVLO threshold, this state

remains for 131,072 clock cycles.

After 1024 or 131,072 cycles (as the case may be), the HiperLCS turns

off the internal pull-up transistor, the soft-start capacitor begins to

charge, the output MOSFETs switch at f

MAX, current in the FEEDBACK

pin diminishes, the frequency begins to drop, and the PSU output rises.

For example, for f

MAX = 800 kHz, the start-up delay after VCC power-up

is 1.3 ms. If IS, or the OV/UV pin are tripped, auto-restart is invoked,

with a restart delay of 164 ms.

The FEEDBACK pin has a current limit equal to the current flowing into

the DT/BF pin. This limits the maximum current that charges the

soft-start capacitor at start-up. If R

START is smaller than that which

allows the FEEDBACK pin current to match the DT/BF pin current at

start-up, an additional delay is introduced. C

START will charge at the

current limit, and switching will only commence when the FEEDBACK

pin voltage drops below 2.0 V. Thus the designer can add an additional

start-up delay if desired.

As the soft-start capacitor continues to charge, the current through

START and thus the FEEDBACK pin decreases, reducing switching

frequency. The output voltage climbs; and when the feedback loop

closes, the optocoupler conducts and starts controlling the switching

frequency thus the output voltage.

Remote-Off

Remote-off can be invoked by pulling down the OV/UV pin to ground,

or by pulling up the IS pin to >0.9 V. Both will invoke a 131,072 cycle

restart cycle. VCC can also be pulled down to shut the device off, but

when it is pulled up, the FEEDBACK pin is pulled up to the VREF pin to

discharge the soft-start capacitor for only 1024 f

MAX clock cycles. If this

scheme is used, the designer must ensure that the time the VCC is

pulled down, plus 1024 cycles, is sufficient to discharge the soft-start

capacitor, or if not, that the resulting lower starting frequency is high

enough so as not to cause excessive primary currents that may cause

the over-current protection to trip.

IS Pin

The IS pin has 2 thresholds: nominally 0.5 V and 0.9 V. The IS pin

can tolerate small negative voltages and currents, and thus does not

need a peak detector or rectifier circuit. The pin has a reverse-biased

diode to ground equivalent circuit, and can tolerate a maximum

negative current of 5 mA. The primary current is sampled by a

primary, B- referenced current sense resistor, or by a capacitor current

divider + current sense resistor combination circuit. In order to limit

the negative current to 5 mA, a current limiting resistor between the

sense resistor and the IS pin is necessary, with a minimum value of

220 Ω. Using the minimum value maximizes the IS pin bypass

capacitor value and thus pin noise rejection, for a given RC pole

frequency. The IS pin will invoke a restart if it sees 7 consecutive

pulses >0.5 V. It will also invoke a restart if a single pulse exceeds

0.9 V. The minimum pulse detection time is nominally 30 ns – i.e. the

pulses must be higher than the threshold voltage for >30 ns.

The “capacitive divider” circuit in Figure 23 reduces power dissipation

and improves efficiency over a simple current sense resistor circuit.

The two capacitors, main resonant capacitor C11, and sense capacitor

C12, form a current divider. The portion of the primary current

routed through C12 is

Consequently, the voltage at the IS pin is equal to

where I

P is the primary current flowing from the HB pin through the

transformer primary. The current in the sense capacitor passes

through sense resistor R11. Resistor R11 is the main means for

tuning current limit. The signal on R11, an AC voltage, passes

through low-pass filter R12 and C7, to the IS pin. Note that R11 is

returned to the GROUND pin and not to SOURCE pin.

PI-6471-052411

2.5

1.5

0.5

3.5

4.5

-6

-2

-4

Time (ms)

-8

-10

Primary Current

Output Voltage

Figure 22. Typical Start-up Waveform. Observe Initial Current Spike ‘A’ to

Ensure it is Below the 1-Cycle Current Limit. A Higher f

MAX Reduces

it. Size the Soft-Start Capacitor so that the Peak of ‘B’ is just Below

the Peak Current at V

BROWNOUT at Full Load.

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