XRT83SL216 datasheet(22/41 Pages) EXAR

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XRT83SL216

PRELIMINARY

16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT

REV. P1.0.3

NOTE: VDD=3.3V ±5%, TA=25°C, Unless Otherwise Specified

2.2

HDB3 Encoder

In single rail mode, the LIU can encode the TPOS input signal to AMI or HDB3 data. If HDB3 encoding is

selected, any sequence with four or more consecutive zeros in the input will be replaced with 000V or B00V,

where "B" indicates a pulse conforming to the bipolar rule and "V" representing a pulse violating the rule. An

example of HDB3 encoding is shown in Table 3.

2.3

Transmit Jitter Attenuator

The XRT83SL216 LIU is ideal for multiplexer or mapper applications where the network data crosses multiple

timing domains. As the higher data rates are de-multiplexed to E1 data, stuffing bits are typically removed

which can leave gaps in the incoming data stream. The JA can be configured in the transmit path with a 32-Bit

or 64-Bit FIFO that is used to smooth the gapped clock into a steady E1 output. The maximum gap width the

JA in the Transmit path can tolerate is shown in Table 4.

NOTE: If the LIU is used in a loop timing system, the JA should be configured in the receive path. See the Receive Section

of this datasheet.

TABLE 2: TIMING SPECIFICATIONS FOR TCLK/TPOS/TNEG

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

TCLK Duty Cycle

TCDU

Transmit Data Setup Time

TSU

Transmit Data Hold Time

THO

TCLK Rise Time (10% to 90%)

TCLKR

TCLK Fall Time (90% to 10%)

TCLKF

TABLE 3: EXAMPLES OF HDB3 ENCODING

NUMBER OF PULSES BEFORE

NEXT 4 ZEROS

Input

0000

HDB3 (Case 1)

Odd

000V

HDB3 (Case 2)

Even

B00V

TABLE 4: MAXIMUM GAP WIDTH FOR MULTIPLEXER/MAPPER APPLICATIONS

FIFO DEPTH

MAXIMUM GAP WIDTH

32-Bit

20 UI

64-Bit

50 UI

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