Data Sheet

LTC4296-1

REGISTER MAP

analog.com

Rev. 0 | 32 of 46

Table 19. PxCFG0 (Register Address 0xx3): Port x Configuration Register 0, Read/Write, Provides Port x Configuration (Continued)

Bit(s)

Name

Description

12

DISABLE_DETECTION_PULLUP

Write 1 to disable the detection pull-up current.

11

TDET_DISABLE

Write 1 to disable the detection timer.

10

FOLDBACK_DISABLE

Write 1 to disable foldback during port inrush in the power-up state.

9

SOFT_START_DISABLE

Write 1 to disable soft-start during port inrush in the power-up state.

8

TOFF_TIMER_DISABLE

Write 1 to disable the tOFF timer to allow the port arbitrarily long time for discharging in the settle-sleep state.

7

TMFVDO_TIMER_DISABLE

Write 1 to disable the tMFVDO timer to prevent the port from shutting off in absence of a valid MFVS.

6

SW_PSE_READY

Write 1 to indicate that the port is ready for detection.

5

SW_POWER_AVAILABLE

Write 1 to indicate that the port is able to source power to the connected PD.

4

UPSTREAM_WAKEUP_DISABLE

Write 1 to disable the upstream (PD initiated) wake-up of the port.

3

DOWNSTREAM_WAKEUP_DISABLE

Write 1 to disable the downstream (PSE initiated) wake-up of the port.

2

SW_PSE_WAKEUP

Write 1 to wake up the port.

1

HW_EN_MASK

Write 0 to mask the AUTO pin.

0

SW_EN

Write 1 to enable the port.

Table 20. PxCFG1 (Address 0xx4): Port x Configuration Register 1, Read/Write, Provides Port x Configuration

Bit(s)

Name

Description

[15:9]

Reserved

Reserved for future use.

8

PREBIAS_OVERRIDE_GOOD

Write 1 to simulate a valid wake-up signature.

[7:6]

TLIM_TIMER_TOP

Write as follows to configure the top-side fault timer (tLIM):

00b = 59.9 ms (default).

01b = 29.9 ms.

10b = 15 ms.

11b = 0.46 ms.

Note that the tLIM timer decrements towards zero in the presence of the fault event and increment towards the configured value

in absence of the fault event. The decrement rate is 8x the increment rate

[5:4]

TOD_TRESTART_TIMER

Write as follows to configure the overload delay timer and restart timer:

00b = default (tOD = 1.1 sec and tRESTART = 551 ms).

01b = 2x of default.

10b = 4x of default.

11b = forever.

[3:2]

TINRUSH_TIMER

Write as follows to configure the tINRUSH timer:

00b = 3.5 ms.

01b = 14 ms.

10b = 56.2 ms (default).

11b = forever.

1

SIG_OVERRIDE_BAD

Write 1 to simulate an invalid detection voltage signature.

0

SIG_OVERRIDE_GOOD

Write 1 to simulate a valid detection voltage signature.

Table 21. PxADCCFG (Register Address 0xx5): Port x ADC Configuration Register, Read/Write, Provides Port x ADC Configuration

Bit(s)

Name

Description

[15:8]

Reserved

Reserved for future use.

[7:0]

MFVS_THRESHOLD

MFVS threshold to be set based on the MFVS Threshold Code = 62.5 x R1 equation. See the Maintain Full Voltage

Signature (MFVS) section for additional information.