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Data Sheet

LTC4296-1

THEORY OF OPERATION

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Rev. 0 | 21 of 46

Autonomous Mode

For applications that do not require classification, the LTC4296-1

can operate in an autonomous mode without a host controller when

the AUTO pin is pulled high. In autonomous mode, the LTC4296-1

powers up any port when a PD presents a valid detection signature.

This mode is ideal for applications that only require a basic detec-

tion. Power-up can be forced, regardless of the detection signature,

by setting the signature override good bit (Register PxCFG1, Bit 0,

SIG_OVERRIDE_GOOD).

PORT STATE DESCRIPTIONS

Overview

Every port in the LTC4296-1 implements the PSE state described in

the usage cases (see the 802.3cg-Compliant PSE section and the

Autonomous Mode section). A detailed description of each state is

provided in the subsequent sections.

Disabled State

A port starts in the disabled state after a power-on or software

reset event. In this state, the high-side MOSFET is turned off,

and the port voltage is discharged to less than VDISABLED with an

internal pull-down. The port remains in this state until it is enabled

by the software enable bit (Register PxCFG0, Bit 0, SW_EN) or if

the AUTO pin is high and not masked (Register PxCFG0, Bit 1,

HW_EN_MASK). Once enabled, the port enters the idle state.

Idle State

In the Idle state, the port output is biased by the LTC4296-1 to

VSLEEP. If the output voltage is in the VSLEEP range, the output

current is less than the IWAKEUP maximum, and the AUTO pin is

high or the software PSE ready is asserted (Register PxCFG0, Bit

6, SW_PSE_READY), the port proceeds to the detection state. If

the port current exceeds IWAKEUP for tLIM_SLEEP, the port enters the

overload state.

Detection State

PD detection is performed in the detection state. During detection, a

probing current, IVALID, is sourced and the port searches for a PD. A

PD not requiring classification presents a valid detection signature

voltage in the range of 4.05 V to 4.55 V when the PSE sources

IVALID. Figure 47 shows a typical valid PD detection sequence.

The PSE must accept a PD detection signature as valid when a

valid detection signature voltage is present for at least tSIG_HOLD

and must reject voltages less than VBAD_LO_PSE (3.7 V) or greater

than VBAD_HI_PSE (5 V), dark shaded regions in Figure 48. The PSE

can accept or reject voltages in the undefined ranges between the

must-reject and must-accept limits (light shaded regions).

A port exits the detection state after tDET unless the detection timer

is disabled (PxCFG0, Bit 11, TDET_DISABLE). If the tDET timer

expires without detecting a valid PD signature, the port enters the

restart state and then returns to the idle state.

For use cases not requiring classification, the following conditions

must be met to proceed to the power-up state:

►

A valid detection signature is found (or Register PxCFG1, Bit 0,

SIG_OVERRIDE_GOOD, is set).

►

The global software power-good bit is set (Register GCFG, Bit 0,

SW_VIN_PGOOD).

►

The port software power available bit is set (Register PxCFG0,

Bit 5, SW_POWER_AVAILABLE). If the port software power

available bit is not set, the port goes to the restart state after

exiting the detection state.

Figure 47. Typical Valid Detection Sequence Waveform

Figure 48. IEEE 802.3bu Signature Voltage Range

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