LT8301 datasheet(23/46 Pages) AD

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Data Sheet

LTC4296-1

THEORY OF OPERATION

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idle state. The tRESTART timer limits are programmable (Register

PxCFG1, Bits[5:4], TOD_TRESTART_TIMER).

Overload State

A current overload fault can occur during any state except the

disabled state or detection state. This fault causes the port to enter

the overload state.

In the overload state, the port high-side MOSFET is turned off, and

the port output voltage is discharged to the VDISABLE range. The

port waits the overload delay time (tOD) before going to the idle

state. The tOD timer limits are programmable (PxCFG1, Bits[5:4],

TOD_TRESTART_TIMER).

Maintain Full Voltage Signature (MFVS)

MFVS detection guarantees that the full operating voltage is applied

only when a PD is connected and requires full power. A PD must

draw more than 11 mA to ensure it continues to receive the full

operating voltage. In the power-on state, a port must consider the

MFVS present when the port current exceeds the maximum hold

current (IHOLD(MAX)) of 10 mA for at least tMFVS. The port MFVS

is absent when the port current drops to less than the minimum

hold current (IHOLD(MIN)) of 2.5 mA for at least tMFVDO. A port can

consider the MFVS present or absent when the port current is in

the IHOLD range (Figure 50). If the MFVS is absent, the port enters

the settle-sleep state and discharges the port output voltage to the

VSLEEP range.

Figure 50. IEEE 802.3bu MFVS Current Ranges

The LTC4296-1 offers a number of advanced power management

features. The WAKEUP pin can be used as a hardware interrupt to

indicate a PD initiated wake-up or to forward a wake-up request,

both of which can be disabled through the SPI. The LTC4296-1 also

has a low current deep sleep mode that is useful in battery-powered

applications when all the ports are either in the disabled or sleep

state.

A port can be forced to stay in the power-on state if the MFVS

is absent by disabling the tMFVDO timer (Register PxCFG0, Bit 7,

TMFVDO_TIMER_DISABLE).

The MFVS threshold of a port is programmable (Register

PxADCCFG, Bits[7:0], MFVS_THRESHOLD). The following equa-

tion gives the optimum code as a function of the high-side sense

resistor, R1, and the value is rounded to the nearest integer:

MFVS Threshold Code = 62.5 × R1

(1)

HOST SERIAL INTERFACE

The LTC4296-1 communicates with the system host using the SPI.

The CS input allows the host to select the end device at a time for

serial communication when multiple end devices share a common

SPI bus.

SPI Clock Phase and Polarity

The LTC4296-1 operates in SPI Mode 3 (SCK polarity (CPOL) = 1,

clock phrase (CPHA) = 0, and idle CLK = 1). Consequently, data on

the SDI must be stable during the rising edge of SCK as shown in

Figure 51 and Figure 52 (write and read, respectively).

Data Transfers

Every command (read or write) is 1 byte long consisting of 7 bits of

address and 1 read and/or write bit. Every register value is 2 bytes

long. The command and data are transferred with the MSB first.

On a write, the data value on the SDI is latched into the device on

the rising edge of the SCK (Figure 51). Similarly, on a read, the

data value output on the SDO is valid during the rising edge of the

SCK and transitions on the falling edge of the SCK (Figure 52). CS

must remain low for the entire duration of a command sequence,

including between a command byte and subsequent data.

PEC Byte

The PEC byte is a cyclic redundancy check (CRC) value calculated

for all the bits in a register group in the order the bits are passed,

using the initial PEC value of 0x41, and this characteristic polyno-

mial, x8 + x2 + x + 1.

To calculate the 8-bit PEC value, take the following steps:

1. Initialize the PEC to 0x41.

2. For each data bit (DIN) coming into the register group, set IN0 =

DIN XOR PEC, Bit 7, and then IN1 = PEC0 XOR IN0, and IN2 =

PEC1 XOR IN0.

3. Update the 8-bit PEC as PEC7 = PEC6, PEC6 = PEC5 …

PEC3 = PEC2, PEC2 = IN2, PEC1 = IN1, and PEC0 = IN0.

4. Go back to Step 2 until all data is shifted. The 8-bit result is the

final PEC byte.

For a given SPI transaction, the PEC byte is calculated over the

entire command byte, which includes the address and a read

and/or write bit, using the previous steps. The PEC byte is then

reinitialized to 0x41 for subsequent data-word reads or writes. The

PEC byte is calculated for each data-word separately.

The LTC4296-1 calculates a PEC byte for any command or data

received and compares it with the PEC byte received following the

command or data. The command or data is regarded as valid only

if the PEC bytes match. For a SPI read operation, the LTC4296-1

attaches the calculated PEC byte at the end of the data it shifts out

on the SDO pin.

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