Data Sheet

LTC4296-1

REGISTER MAP

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Table 9. GFLTEV (Register Address 0x02): Global Fault Event Register, Read/Write 1 to Clear, and Indicates Presence of Global Level Faults (Continued)

Bit(s)

Name

Description

0

LOW_CKT_BRK_FAULT

Set if one or more circuit breakers are tripped in the return path or if there is a fault in the deep sleep return path.

Table 10. GFLTMSK (Register Address 0x03): Global Fault Event Mask Register, Read/Write, Provides Mask for the Global Level Fault Events

Bit(s)

Name

Description

[15:4]

Reserved

Reserved for future use.

3

COMMAND_FAULT

If this bit is cleared, the command interrupt is cleared.

2

PEC_FAULT

If this bit is cleared, the PEC interrupt is cleared.

1

MEMORY_FAULT

If this bit is cleared, the memory interrupt is cleared.

0

LOW_CKT_BRK_FAULT

If this bit is cleared, the return path interrupt is cleared.

GLOBAL STATUS

Table 11. GCAP (Register Address 0x06): Global Capability Register, Read Only, Presents Supported Features of the PoDL Standard

Bit(s)

Name

Description

[15:7]

Reserved

Reserved for future use.

6

SCCP_SUPPORT

Set to 1 if the SCCP is supported. Note that the SCCP is not supported by the LTC4296-1 without external microcontroller support.

5

WAKE_FWD_SUPPORT Set to 1 if wake-up forwarding is supported (wake-up forwarding is supported by the LTC4296-1).

[4:0]

NUMPORTS

Number of PSE ports.

Table 12. GIOST (Register Address 0x07): Global Status Register, Read Only, Presents Status of the Inputs and Outputs

Bit(s)

Name

Description

[15:9]

Reserved

Reserved for future use.

8

PG_OUT4

Status of Port 4 power good.

7

PG_OUT3

Status of Port 3 power good.

6

PG_OUT2

Status of Port 2 power good.

5

PG_OUT1

Status of Port 1 power good.

4

PG_OUT0

Status of Port 0 power good.

3

PAD_AUTO

Status of AUTO pin.

2

PAD_WAKEUP

Status of WAKEUP pin as driven by the host.

1

PAD_WAKEUP_DRIVE

Status of WAKEUP pin as driven by the IC.

0

Reserved

Reserved for future use.

GLOBAL COMMAND

Table 13. GCMD (Register Address 0x08): Global Command Register, Read/Write, Entry Point for the Host to Configure the Chip

Bit(s)

Name

Description

[15:8]

SW_RESET

After writing the reset code (0x73) in this field, the digital logic is reset (software reset).

[7:0]

WRITE_PROTECT

After writing the write unlock key (0x05), write access to all writeable registers is enabled.

After writing the write lock key (0xA0), write access to all writeable registers is disabled.

Write access to this field is always enabled.

CONFIGURATION

Table 14. GCFG (Register Address 0x09): Global Configuration Register, Read/Write, Enables the Host to Configure Global Functions

Bit(s)

Name

Description

[15:6]

Reserved

Reserved for future use.

5

MASK_LOWFAULT

Write 1 to prevent ports from entering overload due to low-side faults.

4

TLIM_DISABLE

Write 1 to disable current-limit timers (tLIM) of all ports.