Electronic Components Datasheet Search
  English  ▼

X  

LPC55S2X Datasheet(PDF) 102 Page - NXP Semiconductors

Part # LPC55S2X
Description  32-bit Arm Cortex®-M33, CASPER, 256 KB SRAM; 512 KB flash, USB HS, Flexcomm Interface, SDIO, 32-bit counter/ timers, SCTimer/PWM, PLU, 16-bit 1.0 Msamples/sec ADC, Comparator, Temperature Sensor, AES, PUF, SHA, CRC, RNG
PDF  140 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

LPC55S2X Datasheet(HTML) 102 Page - NXP Semiconductors

Back Button LPC55S2X Datasheet HTML 98Page - NXP Semiconductors LPC55S2X Datasheet HTML 99Page - NXP Semiconductors LPC55S2X Datasheet HTML 100Page - NXP Semiconductors LPC55S2X Datasheet HTML 101Page - NXP Semiconductors LPC55S2X Datasheet HTML 102Page - NXP Semiconductors LPC55S2X Datasheet HTML 103Page - NXP Semiconductors LPC55S2X Datasheet HTML 104Page - NXP Semiconductors LPC55S2X Datasheet HTML 105Page - NXP Semiconductors LPC55S2X Datasheet HTML 106Page - NXP Semiconductors Next Button
Zoom Inzoom in Zoom Outzoom out
 102 / 140 page
background image
LPC55S2x/LPC552x
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2022. All rights reserved.
Product data sheet
Rev. 2.2 — 8 December 2022
102 of 139
NXP Semiconductors
LPC55S2x/LPC552x
32-bit ARM Cortex-M33 microcontroller
11.14 SD/MMC and SDIO
Table 38. Dynamic characteristics: SD/MMC and SDIO
Tamb = 40 C to +105 C, VDD = 1.8 V to 3.6 V; CL = 10 pF. SAMPLE_DELAY = 0, DRV_DELAY = 0 in the SDDELAY
register, SDIOCLKCTRL = 0x84, sampled at 90 % and 10 % of the signal level, SLEW = 1 ns for SD_CLK pin, SLEW = 1 ns
for SD_DATn and SD_CMD pins. Simulated values in high-speed mode. Not tested in production.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fclk
clock frequency
on pin SD_CLK; data transfer mode
-
-
50
MHz
tsu(D)
data input set-up time
on pins SD_DATn as inputs
15
-
-
ns
on pins SD_CMD as inputs
15
-
-
ns
th(D)
data input hold time
on pins SD_DATn as inputs
0
-
-
ns
on pins SD_CMD as inputs
0
-
-
ns
tv(Q)
data output valid time
on pins SD_DATn as outputs
3
-
7
ns
on pins SD_CMD as outputs
3
-
7
ns
Fig 22. SD/MMC and SDIO timing
002aag204
SD_CLK
SD_DATn (O)
SD_DATn (I)
td(QV)
th(D)
tsu(D)
Tcy(clk)
th(Q)
SD_CMD (O)
SD_CMD (I)



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com