LPC55S69JBD64 datasheet(101/140 Pages) NXP

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LPC55S6x

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Product data sheet

Rev. 2.4 — 8 December 2022

101 of 138

NXP Semiconductors

LPC55S6x

32-bit ARM Cortex-M33 microcontroller

11.13 USART interface

The actual USART bit rate depends on the delays introduced by the external trace, the

external device, system clock (CCLK), and capacitive loading. Excluding delays

introduced by external device and PCB, the maximum supported bit rate for USART

master and slave synchronous mode is 25 Mbit/s. Excluding delays

introduced by external device and PCB, the maximum supported bit rate for USART

master and slave asynchronous mode is 10 Mbit/s.

[1] Based on simulated values. Not tested in production.

Table 38. USART dynamic characteristics[1]

Tamb = 40 C to 105 C; VDD = 1.8 V to 3.6 V; CL = 10 pF balanced loading on all pins; Input slew = 1 ns, SLEW setting =

fast-mode for all pins; Parameters sampled at the 50% level of the rising or falling edge.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

USART master (in synchronous mode)

tsu(D)

data input set-up time

th(D)

data input hold time

tv(Q)

data output valid time

USART slave (in synchronous mode)

tsu(D)

data input set-up time

th(D)

data input hold time

tv(Q)

data output valid time

Fig 21. USART timing

Un_SCLK (CLKPOL = 0)

TXD

RXD

Tcy(clk)

tsu(D) th(D)

tv(Q)

START

BIT0

tvQ)

Un_SCLK (CLKPOL = 1)

START

BIT0

BIT1

aaa-015074

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