Dual Path Lowband RF Receiver

400MHz to 1100MHz

F1130

Datasheet

Glitch-FreeTM, RF Receiver

4

February 8, 2022

F1130 SPECIFICATION

Specifications apply at VCC = +5.00V, TCASE = +25°C, FRF = 900MHz, FIF = 199MHz, FLO = 1099MHz, PLO = 0dBm, For

bypass ON, RF VGA input = +5dBm, for Bypass OFF, RF VGA input = -20dBm/tone, Attenuator = 0dB, STBY_A,

STBY_B = GND unless otherwise noted. Trace, Connector, and external transformer losses are de-embedded

.

Parameter

Symbol

Conditions

Min

Typ

Max

Units

General

Logic Input High

VIH

All Control Pins

1.17

V

Logic Input Low

VIL

All Control Pins

0.67

V

Logic Current

IIH, IIL

All Control Pins

-120

+120

μA

Standby Mode Logic

STBY

STBY = VIH or Floating

Power OFF

STBY = VIL

Power ON

Supply Current

ICC_ON

Bypass OFF, 2 Channels

360

4101

mA

ICC_OFF1

Bypass ON, 1 Channels

(CHA or CHB)

295

330

ICC_OFF2

Bypass ON, 2 Channels

(CHA and CHB)

230

260

ICC_STBY

Standby Mode

20

26

RF Switching time3

τRF

10% to 90% risetime

250

ns

DSA Settling time3

τSET

10% to 90% risetime

100

ns

Turn ON time3

τON

10% to 90% risetime

225

ns

Turn OFF time3

τOFF

10% to 90% risetime

25

ns

Control Interface

SPIBIT

14

bit

Serial Clock Speed

SPICLK

24

MHz

Note 1: Items in min/max columns in bold italics are Guaranteed by Test.

Note 2: Items in min/max columns that are not bold/italics are Guaranteed by Design Characterization.

Note 3: Speeds are measured after SPI programming is completed (data latched with LE = HIGH).

Note 4: Gain across the entire frequency band is affected by the inclusion of the RF switch.