Dual Path Lowband RF Receiver

400MHz to 1100MHz

F1130

Datasheet

Glitch-FreeTM, RF Receiver

9

February 8, 2022

PIN 8 LATCH ENABLE (LE):

When LE is high (> VIH), the CLK input is disabled. Renesas recommends keeping LE high to reduce F1130

sensitivity to CLK bus noise when SPI is not being programmed. When LE is low (< VIL), the DATA word can be

programmed into the shift registers. The programmed word is then latched into F1130 on the LE rising edge (refer to

Figure 1). End of data occurs after 14th bit.

DEFAULT REGISTER SETTING:

After power on, the default setting for the VGA is Bypass OFF mode with attenuation set to 30 dB. This means the

amplifier is in the signal path with maximum attenuation.

TYPICAL OPERATING CONDITIONS (TOC)

Unless otherwise noted for the TOC graphs on the following pages, the following conditions apply.

• V

CC = +5.00 V

• T

CASE = +25 °C

• F

RF = 900 MHz

• F

IF = 199 MHz

• F

LO = 1100 MHz

• P

LO = 0 dBm

• RF VGA output = -5 dBm/tone

• RF Mixer output = 0 dBm/tone

• Attenuator = 0 dB

• STBY_A, STBY_B = GND