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QL3025 pASIC 3 FPGA Data Sheet Rev E
Architecture Overview
The QL3025 is a 25,000 usable PLD gate member of the pASIC 3 family of FPGAs.
pASIC 3 FPGAs are fabricated on a 0.35
µm four-layer metal process using QuickLogic's
patented ViaLink technology to provide a unique combination of high performance, high
density, low cost, and extreme ease-of-use.
The QL3025 contains 672 logic cells. With a maximum of 204 I/Os, the QL3025 is
available in 144-pin TQFP, 208-pin PQFP, and 256-pin PBGA packages.
Software support for the complete pASIC 3 family, including the QL3025, is available
through three basic packages. The turnkey QuickWorks package provides the most
complete FPGA software solution from design entry to logic synthesis, to place and route,
to simulation. The QuickToolsTM for Workstations package provides a solution for designers
who use Cadence, ExemplarTM, Mentor, Synopsys, Synplicity, ViewlogicTM, AldecTM,
or other third-party tools for design entry, synthesis, or simulation.
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