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© 2002 QuickLogic Corporation
www.quicklogic.com
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QL3025 pASIC 3 FPGA Data Sheet Rev E
Power-up Sequencing
Figure 5: Power-up Requirements
The following requirements must be met when powering up the device (refer to Figure 5):
•
When ramping up the power supplies keep (V
CCIO -VCC)MAX ≤ 500 mV. Deviation from
this recommendation can cause permanent damage to the device.
•
V
CCIO must lead VCC when ramping the device.
•
The power supply must take greater than or equal to 400 µs to reach V
CC. Ramping to
V
CC/VCCIO earlier than 400 µs can cause the device to behave improperly.
An internal diode is present in-between V
CC and VCCIO, as shown in Figure 6.
Figure 6: Internal Diode Between V
CC and VCCIO
V
CCIO
V
CC
(V
CCIO -VCC)MAX
Time
400 us
V
CC
V CC
V CCIO
Internal Logic
Cells, RAM
blocks, etc
IO Cells
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