© 2002 QuickLogic Corporation
www.quicklogic.com
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Device Highlights
High Performance & High Density
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25,000 Usable PLD Gates with 204 I/Os
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300 MHz 16-bit Counters,
400 MHz Datapaths
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0.35
µm four-layer metal non-volatile
CMOS process for smallest die sizes
Easy to Use / Fast Development
Cycles
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100% routable with 100% utilization and
complete pin-out stability
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Variable-grain logic cells provide high
performance and 100% utilization
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Comprehensive design tools include high
quality Verilog/VHDL synthesis
Advanced I/O Capabilities
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Interfaces with both 3.3 V and 5.0 V devices
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PCI compliant with 3.3 V and 5.0 V buses
for -1/-2/-3/-4 speed grades
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Full JTAG boundary scan
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I/O Cells with individually controlled
Registered Input Path and Output Enables
Total of 204 I/O Pins
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196 bidirectional input/output pins,
PCI-compliant for 5.0 V and 3.3 V buses for
-1/-2/-3/-4 speed grades
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Four High Drive input-only pins
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Four High Drive input-only/distributed
network pins
Four Low-Skew Distributed
Networks
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Two array clock/control networks available
to the logic cell flip-flop clock, set and reset
inputs — each driven by an input-only pin
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Two global clock/control networks available
to the logic cell; F1, clock set, reset inputs
and the input, I/O register clock, reset, and
enable inputs as well as the output enable
control — each driven by an input-only or
I/O pin, or any logic cell output or I/O cell
feedback
High Performance
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Input + logic cell + output total delays
under 6 ns
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Data path speeds over 400 MHz
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Counter speeds over 300 MHz
Figure 1: 672 pASIC 3 Logic Cells
QL3025 pASIC 3 FPGA Data Sheet
25,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance
and High Density
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