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QL3025 Datasheet(PDF) 3 Page - List of Unclassifed Manufacturers

Part # QL3025
Description  25,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density
PDF  17 Pages
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Manufacturer  ETC1 [List of Unclassifed Manufacturers]
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QL3025 Datasheet(HTML) 3 Page - List of Unclassifed Manufacturers

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© 2002 QuickLogic Corporation
www.quicklogic.com
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QL3025 pASIC 3 FPGA Data Sheet Rev E
Electrical Specifications
AC Characteristics at V
CC = 3.3 V, TA = 25°C (K = 1.00)
To calculate delays, multiply the appropriate K factor from Table 7 by the numbers provided
in Table 1 through Table 5.
Table 1: Logic Cells
Symbol
Parameter
Propagation Delays (ns) Fanouta
a. Stated timing for worst case Propagation Delay over process variation at V
CC = 3.3 V and
TA = 25
°C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage, and temperature
settings as specified in
Table 7.
1
2
3
4
8
t
PD
Combinatorial Delay b
b. These limits are derived from a representative selection of the slowest paths through the
pASIC 3 logic cell including typical net delays. Worst case delay values for specific paths should
be determined from timing analysis of your particular design.
1.4
1.7
1.9
2.2
3.2
tSU
Setup Time b
1.7
1.7
1.7
1.7
1.7
tH
Hold Time
0.0
0.0
0.0
0.0
0.0
t
CLK
Clock to Q Delay
0.7
1.0
1.2
1.5
2.5
tCWHI
Clock High Time
1.2
1.2
1.2
1.2
1.2
tCWLO
Clock Low Time
1.2
1.2
1.2
1.2
1.2
t
SET
Set Delay
1.0
1.3
1.5
1.8
2.8
tRESET
Reset Delay
0.8
1.1
1.3
1.6
2.6
tSW
Set Width
1.9
1.9
1.9
1.9
1.9
t
RW
Reset Width
1.8
1.8
1.8
1.8
1.8
Table 2: Input-Only/Clock Cells
Symbol
Parameter
Propagation Delays (ns) Fanout a
a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and
TA = 25
°C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage, and tempera-
ture settings as specified in
Table 7.
1
2
3
4
8
12
24
t
IN
High Drive Input Delay
1.5
1.6
1.8
1.9
2.4
2.9
4.4
tINI
High Drive Input, Inverting Delay
1.6
1.7
1.9
2.0
2.5
3.0
4.5
t
ISU
Input Register Set-Up Time
3.1
3.1
3.1
3.1
3.1
3.1
3.1
t
IH
Input Register Hold Time
0.0
0.0
0.0
0.0
0.0
0.0
0.0
tlCLK
Input Register Clock To Q
0.7
0.8
1.0
1.1
1.6
2.1
3.6
t
lRST
Input Register Reset Delay
0.6
0.7
0.9
1.0
1.5
2.0
3.5
t
lESU
Input Register clock Enable Set-Up Time
2.3
2.3
2.3
2.3
2.3
2.3
2.3
tlEH
Input Register Clock Enable Hold Time
0.0
0.0
0.0
0.0
0.0
0.0
0.0



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