4
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© 2002 QuickLogic Corporation
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QL3025 pASIC 3 FPGA Data Sheet Rev E
Table 3: Clock Cells
Symbol
Parameter
Propagation Delays (ns) Loads per Half Column a
a. The array distributed networks consist of 40 half columns and the global distributed networks con-
sist of 44 half columns, each driven by an independent buffer. The number of half columns used
does not affect clock buffer delay. The array clock has up to eight loads per half column. The glo-
bal clock has up to 11 loads per half column.
1
2
3
4
8
10
11
tACK
Array Clock Delay
1.2
1.2
1.3
1.3
1.5
1.6
1.7
t
GCKP
Global Clock Pin Delay
0.7
0.7
0.7
0.7
0.7
0.7
0.7
tGCKB
Global Clock Buffer Delay
0.8
0.8
0.9
0.9
1.1
1.2
1.3
Table 4: Input-Only I/O Cells
Symbol
Parameter
Propagation Delays (ns) Fanout a
a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and
TA = 25
°C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage, and temperature
settings as specified in
Table 7.
1
2
3
4
8
10
tI/O
Input Delay (bidirectional pad)
1.3
1.6
1.8
2.1
3.1
3.6
t
ISU
Input Register Set-Up Time
3.1
3.1
3.1
3.1
3.1
3.1
tIH
Input Register Hold Time
0.0
0.0
0.0
0.0
0.0
0.0
tlOCLK
Input Register Clock To Q
0.7
1.0
1.2
1.5
2.5
3.0
t
lORST
Input Register Reset Delay
0.6
0.9
1.1
1.4
2.4
2.9
tlESU
Input Register clock Enable Set-Up Time
2.3
2.3
2.3
2.3
2.3
2.3
t
lEH
Input Register Clock Enable Hold Time
0.0
0.0
0.0
0.0
0.0
0.0
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