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68HC705JB2 Datasheet(PDF) 87 Page - NXP Semiconductors

Part # 68HC705JB2
Description  Industry standard M68HC05 CPU core
PDF  128 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

68HC705JB2 Datasheet(HTML) 87 Page - NXP Semiconductors

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August 28, 1998
GENERAL RELEASE SPECIFICATION
UNIVERSAL SERIAL BUS MODULE
REV 1.1
10-19
10.5.1 USB Address Register (UADDR)
USBEN — USB Module Enable
This read/write bit enables and disables the USB module and the USB pins.
When USBEN is clear, the USB module will not respond to any tokens. Reset
clears this bit.
1 =
USB function enabled
0 =
USB function disabled
UADD6-UADD0 — USB Function Address
These bits specify the USB address of the device. Reset clears these bits.
10.5.2 USB Interrupt Register 0 (UIR0)
TXD0F — Endpoint 0 Data Transmit Flag
This read only bit is set after the data stored in Endpoint 0 transmit buffers has
been sent and an ACK handshake packet from the host is received. Once the
next set of data is ready in the transmit buffers, software must clear this flag by
writing a logic 1 to the TXD0FR bit. To enable the next data packet
transmission, TX0E must also be set. If TXD0F bit is not cleared, a NAK
handshake will be returned in the next IN transaction.
Reset clears this bit. Writing a logic 0 to TXD0F has no effect.
1 =
Transmit on Endpoint 0 has occurred
0 =
Transmit on Endpoint 0 has not occurred
RXD0F — Endpoint 0 Data Receive Flag
This read only bit is set after the USB module has received a data packet and
responded with an ACK handshake packet. Software must clear this flag by
writing a logic 1 to the RXD0FR bit after all of the received data has been read.
Software must also set RX0E bit to one to enable the next data packet
reception. If RXD0F bit is not cleared, a NAK handshake will be returned in the
next OUT transaction.
Reset clears this bit. Writing a logic 0 to RXD0F has no effect.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
UADDR
R
USBEN
UADD6
UADD5
UADD4
UADD3
UADD2
UADD1
UADD0
$0038
W
reset
⇒
00000000
Figure 10-20. USB Address Register (UADDR)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
UIR0
R
TXD0F
RXD0F
RSTF
SUSPND
TXD0IE
RXD0IE
00
$0039
W
TXD0FR
RXD0FR
reset
⇒
00000000
= Unimplemented
Figure 10-21. USB Interrupt Register 0 (UIR0)
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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