ADF4368 datasheet(42/54 Pages) AD

42 / 54 page

Data Sheet

ADF4368

analog.com

Rev. 0 | 42 of 54

Address: 0x2B, Reset: 0x83, Name: REG002B

Figure 90.

Table 59. Bit Descriptions for REG002B

Bits

Bit Name

Description

Reset

Access

PD_ALL

Main Power Down.

0x1

R/W

0: Normal Operation.

1: Power Down.

REG2B_RSV4

Reserved.

0x0

R/W

REG2B_RSV3

Reserved.

0x0

R/W

REG2B_RSV2

Reserved.

0x0

R/W

PD_LD

Power Down the Lock Detector.

0x0

R/W

0: Normal Operation.

1: Power Down the Lock Detector.

REG2B_RSV1

Reserved.

0x0

R/W

PD_CLKOUT1

Power Down CLK1 Output Buffer.

0x1

R/W

0: Normal Operation.

1: Power Down CLK1 Output.

PD_CLKOUT2

Power Down CLK2 Output Buffer.

0x1

R/W

0: Normal Operation.

1: Power Down CLK2 Output.

Address: 0x2C, Reset: 0x00, Name: REG002C

Figure 91.

Table 60. Bit Descriptions for REG002C

Bits

Bit Name

Description

Reset

Access

[7:5]

LDWIN_PW

Lock Detector Pulse Window Width. The details are given in Table 14.

0x0

R/W

[4:0]

LD_COUNT

Number of PFD Cycles Before LD Goes High. Cycles =

24× 2LD_COUNT+3

if LD_COUNT is even

32× 2LD_COUNT−1+3

if LD_COUNT is odd

0x0

R/W

Address: 0x2D, Reset: 0x00, Name: REG002D

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