COMMERCIALTEMPERATURERANGE

IDTCV128

1-TO-12DIFFERENTIALCLOCKBUFFER

3

PIN DESCRIPTION

Pin Name

Type

Pin #

Description

CLK_IN, CLK_IN#

IN

2, 3

0.7vDifferentialinput

DIF_[9:0] & DIF_[9:0]#

OUT

6, 7, 9, 10, 13, 14, 16,

0.7VDifferentialclockoutputs,gearedtoaratiooftheinputclock

17, 19, 20, 24, 25, 32, 33,

35, 36, 39, 40, 42, 43

DIF & DIF# [11:10]

OUT

47, 48, 51, 52

0.7VDifferentialclockoutputs,whichcanbeconfiguredtobe1:1insteadofgeared.Default

isgearedsameas0-9outputs.

OE_[9:0]#

IN

5, 8, 15, 18, 21, 26,

3.3VLVTTLactiveLOWinputforenablingcorrespondingdifferentialoutputclock.Clocks

31, 34, 41, 44

also can be disabled via SMBus registers

OE _10_11#

IN

53

3.3VLVTTLactivelowinputforenablingboth DIF10and11differentialoutputclocks.Clocks

also can be disabled via SMBus registers individually.

HIGH_BW#

IN

1

3.3 V LVTTL input for selecting the PLL bandwidth. 0 = HIGH BW, 1 = LOW BW.

SCL

IN

29

SMBus slave clock input

SDA

I/O, OC

28

Open collector SMBus data

IREF

IN

54

Aprecisionresistorisattachedtothispintosetthedifferentialoutputcurrent

SA_[0:1]

IN

4, 27

3.3V LVTTL input selecting the address. SA_[2:0] set device SMBus address.

(1)

SA_2/PLL_BYPASS#

IN

30

3.3VLVTTLinput forPLLbypassandSMBusaddress.0=PLLbypassmode;1=PLLmode

FS_A

IN

46

3.3VLVTTLinputtoestablishaHIGH(>200Mhz)orLOWfrequency(<200Mhz)range

VTT_PWRGD#/PWRDWN

IN

45

3.3 V LVTTL input to power up or power down the device.

INDEX BLOCK WRITE PROTOCOL

Bit

# of bits

From

Description

1

1

Master

Start

2-9

8

Master

See SMBus Address Mode table

10

1

Slave

Ack (Acknowledge)

11-18

8

Master

Registeroffsetbyte(startingbyte)

19

1

Slave

Ack (Acknowledge)

20-27

8

Master

Byte count, N (0 is not valid)

28

1

Slave

Ack (Acknowledge)

29-36

8

Master

first data byte (Offset data byte)

37

1

Slave

Ack (Acknowledge)

38-45

8

Master

2nd data byte

46

1

Slave

Ack (Acknowledge)

:

Master

Nth data byte

Slave

Acknowledge

Master

Stop

INDEX BLOCK READ PROTOCOL

Master can stop reading any time by issuing the stop bit without waiting

until Nth byte (byte count bit30-37).

Bit

# of bits

From

Description

1

1

Master

Start

2-9

8

Master

See SMBus Address Mode table

10

1

Slave

Ack (Acknowledge)

11-18

8

Master

Registeroffsetbyte(startingbyte)

19

1

Slave

Ack (Acknowledge)

20

1

Master

RepeatedStart

21-28

8

Master

See SMBus Address Mode table

29

1

Slave

Ack (Acknowledge)

30-37

8

Slave

Byte count, N (block read back of N

bytes)

38

1

Master

Ack (Acknowledge)

39-46

8

Slave

first data byte (Offset data byte)

47

1

Master

Ack (Acknowledge)

48-55

8

Slave

2nd data byte

Ack (Acknowledge)

:

Master

Ack (Acknowledge)

Slave

Nth data byte

Notacknowledge

Master

Stop

INDEX BYTE WRITE

Setting bit[11:18] = starting address, bit[20:27] = 01h.

INDEX BYTE READ

Setting bit[11:18] = starting address. After reading back the first data byte,

masterissuesStopbit.

NOTE:

(1) The SA_2 pin shares functionality with PLL_bypass# mode

setting. The shared function restricts the device addresses that

correspond to SA_2 =0 as setting the buffer device in

PLL_Bypass#.