COMMERCIALTEMPERATURERANGE

10

IDTCV128

1-TO-12DIFFERENTIALCLOCKBUFFER

PWRDWN FUNCTIONALITY

VTT_PWRGD#/PWRDWN

DIF

DIF#

0

Normal

Normal

1

Float

Float

BUFFER POWER-UP STATE MACHINE(1)

NOTE:

1. The total power up latency from power on to all outputs active must be less than 1ms

(assuming a valid clock is present on CLK_IN input). If power is valid and PWRDWN is

de-asserted but no input clocks are present on the CLK_IN input, DIF clocks must remain

disabled. Only after valid input clocks are detected, valid power, PWRDWN# de-asserted

with the PLL locked/stable and the DIF outputs enabled (doesn't apply to bypass mode).

State

Description

State0

Poweroff

State1

After3.3Vsupplyisdetectedtoriseabove1.8-2V,the

bufferentersstate1andinitiatesa0.2ms-0.3msdelay.The

totalpoweruplatencyfrompowerontoalloutputsactive

mustbelessthan1ms(assumeSRC_INisavailable)

State2

BufferwaitsforavalidclockontheSRC_INinputand

PDde-assertion.

State3

Only after SRC_IN and power valid, PD de-asserted

with the current mirror stable, or PLL lock, the DIF

outputsareenabled

BUFFER POWER-UP STATE DIAGRAM

S1

Delay

>0.25 ms

S0

Power Off

S2

Wait for input

clock and

de-assertion

PWRDWN#

S3

Normal

Operation

No Input Clock

PWRDWN# Asserted