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CV128 Datasheet(PDF) 8 Page - Renesas Technology Corp |
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CV128 Datasheet(HTML) 8 Page - Renesas Technology Corp |
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8 / 13 page ![]() COMMERCIALTEMPERATURERANGE 8 IDTCV128 1-TO-12DIFFERENTIALCLOCKBUFFER OUTPUT RELATIONAL TIMING PARAMETERS Group Parameter Min. Typ. Max. CLK_IN, DIF [x:0] Input to Output Skew in PLL mode (1:1 only) 0ps --- 20% of period CLK_IN, DIF [x:0] Input to Output Skew in non PLL mode (1:1 only) 3ns --- 40% of period DIF DIFF[x:0] Pin-to-Pin Skew (output within same group) 0ps --- 50 ps DIF [9:0] - DIF [11:10] Additive skew between pin groups (group of 2 and group of 10) 0ps --- 75 ps DIF Jitter, Cycle_cycle(1) 0ps --- 50ps DIF AccumulatedDifferentialPhaseJitter -100ps --- +100ps PLL BANDWIDTH AND PEAKING Group Parameter Min. Typ. Max. Unit DIF PLL Peaking (HIGH_BW# = 0) --- 1 2 dB DIF PLL Peaking (HIGH_BW# = 1) --- 1 2 dB DIF PLL Bandwidth (HIGH_BW# = 0) 2 3 4 MHz DIF PLL Bandwidth (HIGH_BW# = 1) 0.7 1 1.4 MHz DIF Outputphasejitterimpact 0ps --- --- ps (PCIe: including BW 1.5-22Mhz) --- --- 85 ps (FBD/CSI: including BW 11-33Mhz) --- --- 40 ps NOTE: 1. Bypass mode, additive. |
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