COMMERCIALTEMPERATURERANGE

IDTCV128

1-TO-12DIFFERENTIALCLOCKBUFFER

1

JUNE 29, 2007

IDTCV128

COMMERCIAL TEMPERATURE RANGE

1-TO-12 DIFFERENTIAL

CLOCK BUFFER

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

© 2005 Integrated Device Technology, Inc.

DSC-6743/A

DESCRIPTION:

TheCV128differentialbuffercomplieswithIntelDB1200Grev.0.5, andis

designedtoworkinconjunctionwiththemainclockofCK409,CK410/CK410M

and CK410B etc., PLL is off in bypass mode and no clock detect.

FEATURES:

• Compliant with Intel DB1200G rev. 0.5

• DIF Clock Support

− 12differential clock output pairs @ 0.7 V

− 50 ps skew performance (same gear)

• OE pin Control of All Outputs

• 3.3 V Operation

• Gear Ratio supporting generation of clocks at a different

frequency ratioed from the input.

• Split outputs supporting options of 2 outputs @1:1 and

remaining 10 pairs at an alternate gear

• Pin level OE control of individual outputs

• Multiple output frequency options up to 400Mhz as a gear ratio

of input clocks of 100-400Mhz

• Output is HCSL compatible

• SMBus Programmable configurations

• PLL Bypass Configurable

• SMBus address configurable to allow multiple buffer control in

a single control network

• Programmable Bandwidth

• Glitchfree transition between frequency states

• Available in SSOP and TSSOP packages

DIF_0

DIF_0#

DIF_1

DIF_1#

DIF_2

DIF_2#

DIF_3

DIF_3#

DIF_4

DIF_4#

DIF_5

DIF_5#

DIF_6

DIF_6#

DIF_7

DIF_7#

DIF_8

DIF_8#

DIF_9

DIF_9#

DIF_10

DIF_10#

DIF_11

DIF_11#

PLL

Output

Buffer

SCL

SDA

CLK_IN#

CLK_IN

Output

Control

HIGH_BW#

SA_2/PLL/BYPASS#

OE[9:0]#

VTT_PWRGD#/PWRDWN

SM Bus

Controller

OE_10_11#

FUNCTIONAL BLOCK DIAGRAM