84021 datasheet(4/20 Pages) RENESAS

4 / 20 page

84021 Data Sheet

260MHz, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER

84021 Rev E 9/23/15

Table 2. Pin Characteristics

Function Tables

Table 3A. Parallel and Serial Mode Function Table

NOTE:

L = LOW

H = HIGH

X = Don’t care

 = Rising edge transition

 = Falling edge transition

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

CIN

Input Capacitance

4pF

CPD

Power Dissipation Capacitance

(per output)

VDDO = 3.465V

VDDO = 2.625V

VDDO = 1.89V

RPULLUP

Input Pullup Resistor



RPULLDOWN

Input Pulldown Resistor



ROUT

Output Impedance

VDDO = 3.3V ± 5%



VDDO = 2.5V ± 5%



VDDO = 1.8V ± 5%



Inputs

Conditions

nP_LOAD

S_LOAD

S_CLOCK

S_DATA

Reset. Forces outputs LOW.

Data

Data on M and N inputs passed directly to the M divider and

N output divider. TEST output forced LOW.



Data

Data is latched into input registers and remains loaded until

next LOW transition or until a serial event occurs.



Data

Serial input mode. Shift register is loaded with data on

S_DATA on each rising edge of S_CLOCK.



LData

Contents of the shift register are passed to the M divider and

N output divider.



Data

M divider and N output divider values are latched.

Parallel or serial input do not affect shift registers.



Data

S_DATA passed directly to M divider as it is clocked.

84021 Datasheet(PDF) 4 Page - Renesas Technology Corp

84021 Datasheet(HTML) 4 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Datasheet Download

Link URL