84021 Data Sheet

260MHz, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER

84021 Rev E 9/23/15

10

©2015 Integrated Device Technology, Inc

Table 7C. AC Characteristics, VDD = 3.3V±5%, VDDO = 1.8V±5%, TA = 0°C to 70°C

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium

has been reached under these conditions.

NOTE 1: Jitter performance using XTAL inputs.

NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.

NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

fOUT

Output Frequency

103.3

260

MHz

tjit(per)

Period Jitter, RMS; NOTE 1, 2

N = 3

9.4

13.2

ps

N = 4

10.8

19.6

ps

N = 5

12.7

32.5

ps

N = 6

13.4

25.4

ps

M=40, N=4, 16.667MHz XTAL,

fOUT=166.67MHz

5.4

8.3

ps

M=40, N=5, 16.667MHz XTAL,

fOUT=133.33MHz

5.1

8.8

ps

tsk(o)

Output Skew; NOTE 2, 3

90

ps

tR / tF

Output Rise/Fall Time

20% to 80%

100

800

ps

tS

Setup Time

M, N to nP_LOAD

5

ns

S_DATA to S_CLOCK

5

ns

S_CLOCK to S_LOAD

5

ns

tH

Hold Time

M, N to nP_LOAD

5

ns

S_DATA to S_CLOCK

5

ns

S_CLOCK to S_LOAD

5

ns

odc

Output Duty Cycle

N

 340

60

%

M=40, N=4, 16.667MHz XTAL,

fOUT=166.67MHz

44

56

%

M=40, N=5, 16.667MHz XTAL,

fOUT=133.33MHz

48

52

%

tLOCK

PLL Lock Time

1ms