84021 Data Sheet

260MHz, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER

84021 Rev E 9/23/15

9

©2015 Integrated Device Technology, Inc

Table 7B. AC Characteristics, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C to 70°C

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium

has been reached under these conditions.

NOTE 1: Jitter performance using XTAL inputs.

NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.

NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

fOUT

Output Frequency

103.3

260

MHz

tjit(per)

Period Jitter, RMS; NOTE 1, 2

N = 3

11.4

18.8

ps

N = 4

13.3

28.3

ps

N = 5

16.0

39.8

ps

N = 6

19.2

32.4

ps

M=40, N=4, 16.667MHz XTAL,

fOUT=166.67MHz

4.3

6.2

ps

M=40, N=5, 16.667MHz XTAL,

fOUT=133.33MHz

4.5

7.7

ps

tsk(o)

Output Skew; NOTE 2, 3

90

ps

tR / tF

Output Rise/Fall Time

20% to 80%

100

800

ps

tS

Setup Time

M, N to nP_LOAD

5

ns

S_DATA to S_CLOCK

5

ns

S_CLOCK to S_LOAD

5

ns

tH

Hold Time

M, N to nP_LOAD

5

ns

S_DATA to S_CLOCK

5

ns

S_CLOCK to S_LOAD

5

ns

odc

Output Duty Cycle

N

 344

56

%

M=40, N=4, 16.667MHz XTAL,

fOUT=166.67MHz

45

55

%

M=40, N=5, 16.667MHz XTAL,

fOUT=133.33MHz

47

53

%

tLOCK

PLL Lock Time

1ms