DA7218 datasheet(61/198 Pages) RENESAS

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DA7218

Ultra-Low Power Stereo Codec

Datasheet

Revision 3.4

24-Dec-2021

CFR0011-120-00

61 of 197

● PLL_INTEGER holds the seven integer bits

● PLL_FRAC_BOT holds the top bits (MSB) of the fractional part of the divisor

● PLL_FRAC_BOT holds the bottom bits (LSB) of the fractional part of the divisor

9.5.3

Example Calculation of the Feedback Divider Setting:

Example: A codec operating with a sample rate (FS) = 48 kHz and a reference input clock frequency

of 12.288 MHz. The required output frequency is 98.304 MHz.

The reference clock input = 12.288 MHz, which falls in the range 10-20 MHz, so pll_indiv must be set

to 0b010 dividing the reference input frequency by 4 (see Table 48).

The formula for calculating the feedback divider is:

Feedback divider (F) = VCO output frequency * input divider (pll_indiv) / reference input clock

Therefore Feedback divider (F) = (98.304 * 4) / 12.288 = 32

So:

● pll_fbdiv_integer (holding the seven integer bits) = 0x20

● pll_fbdiv_frac_top (holding the top bits (MSB) of the fractional part of the divisor) = 0x00

● pll_fbdiv_frac_bot (holding the bottom bits (LSB) of the fractional part of the divisor) = 0x00

Table 48 shows example register settings that will configure the PLL when using a 13 MHz, 15 MHz

or 19.2 MHz clock. Note that any MCLK input frequency between 2 MHz and 54 MHz is supported.

pll_indiv must be used to reduce the PLL reference frequency to the usable range of 2 MHz to 5 MHz

as shown in Table 48.

Table 48: Example PLL Configurations

MCLK Input

Frequency

(MHz)

System Clock

Frequency

(MHz)

pll_mode

PLL_FRAC_TOP

PLL_FRAC_BOT

PLL_INTEGER

11.2896

0x01

0x19

0x45

0x1B

12.288

0x01

0x07

0xEA

0x1E

11.2896

0x01

0x02

0xB4

0x18

12.288

0x01

0x06

0xDC

0x1A

19.2

11.2896

0x01

0x1A

0x1C

0x12

19.2

12.288

0x01

0x0F

0x5C

0x14

9.5.4

Sample Rate Matching PLL Mode (DAI Slave)

Sample rate matching (SRM) mode enables the PLL output clock to be synchronized to the incoming

WCLK signal on the DAI. The SRM PLL mode is enabled by setting pll_mode = 10.

When using the DAI in slave mode with the SRM enabled, removing and re-applying the DAI

interface word clock WCLK may cause the PLL lock to be lost. To re-lock the PLL disable the SRM

(pll_mode = 00), reset the PLL by re-writing to register PLL_INTEGER, and then re-enable the SRM

(pll_mode = 10) after the DAI WCLK has been reapplied.

When switching sample rates between 44.1 kHz and 48 kHz (or between the multiples of these

sample rates), SRM must be disabled then re enabled using register bit pll_mode.

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