DA7218 datasheet(97/198 Pages) RENESAS

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DA7218

Ultra-Low Power Stereo Codec

Datasheet

Revision 3.4

24-Dec-2021

CFR0011-120-00

97 of 197

Table 104: DAI_CLK_MODE (Page 0: 0x00000090)

Bit

Mode

Symbol

Description

Reset

R/W

dai_clk_en

DAI master mode control

0 = Slave mode (BCLK/WCLK inputs)

1 = Master mode (BCLK/WCLK outputs)

0x0

R/W

dai_wclk_tri_state

WCLK tri-state control

0 = WCLK state set by the dai_clk_en (WCLK is set as the

output in master mode, and as the input in slave mode)

1 = WCLK forced as an input

0x0

R/W

dai_wclk_pol

DAI word clock polarity control

0 = Normal polarity

1 = Inverted polarity

0x0

R/W

dai_clk_pol

DAI bit clock polarity control

0 = Normal polarity

1 = Inverted polarity

0x0

1:0

R/W

dai_bclks_per_wclk

Number of BCLK cycles per WCLK period in DAI master

mode

00 = 32 BCLK cycles per WCLK

01 = 64 BCLK cycles per WCLK

10 = 128 BCLK cycles per WCLK

11 = 256 BCLK cycles per WCLK

0x1

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