January 28, 2014

6

IDTP9167

Advanced Datasheet

PIN DESCRIPTION

Table 5 – 12-ld DFN Pin Functions by Pin Number

NUMBER LABEL TYPE DESCRIPTION

1

DIF

I

Digital interface to the host PMIC:

1.8V logic input

2

SGND

A

DIF/DIO signal ground reference:

Connect directly to ground plane

3

RSET

A

RSET resistor connection:

Connect to device identification resistor

4

LX

A

Switching node inductor connection:

Connect to either 0.47µH or 1µH inductor depending on application

5

6

7

PGND

A

Device ground:

Connect pins to EPAD ground connection directly below the device

8

9

PVIN

A

Main supply input:

Connect 2x10µF capacitors directly between PVIN & PGND pins (no Via)

Capacitor may be connected to ground plane instead when PVIN supply plane is stacked adjacent to the

ground plane. Use at least 4 Vias for each capacitor connection.

10

VPG

A

High-side Regulator output capacitor connection:

Connect 1.0µF capacitor directly between VPG & PVIN pin (no Via)

11

VSYS

A

5V system supply input:

Connect 4.7µF capacitor directly between VSYS & PGND pins (no Via)

12

DIO

IO

Digital interface to the host PMIC:

Bi-directional 1.8V logic input & open-drain output

13

EPAD

A

Thermal ground:

At least 10 Vias should be used to connect the EPAD to the ground plane directly below the device