January 28, 2014

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IDTP9167

Advanced Datasheet

DIF Signal Integrity Calibration

Depending on the number of DPUs attached, the host automatically configures its DIO and DIF I/O drivers to provide the best

signal quality. Varying line capacitance can change the rise and fall times of the DIF clock pulses and distort the perceived

duty-cycle of the signal, which represents the output current. To minimize this distortion, the DIF channel is calibrated at start-

up and re-calibrated whenever possible to ensure the control transfer function is maintained in each of the DPUs across all

bus loading conditions. As a result, the individual DPUs could be located away from the host PMIC, virtually anywhere on the

board where space and thermal dissipation allows.

PHASE ACTIVATION AND PHASE SHEDDING CONTROL

Individual DPU phases are automatically shut off sequentially, starting with the highest ID first, as load current demand

decreases. When load demand returns, all phases will be switched-on at the same time to minimize the output voltage droop

due to the load step. Both current and time hysteresis are built into the phase activation/shedding decision circuitry in the host

PMIC to ensure stable operation. Phase activation and phase shedding control is achieved by specific pulse detection on the

DIO line. Phase-shedding is not supported when the DPUs are connected to the host PMIC’s integrated controller.

PFM MODE SUPPORT

When the IDTP9167 DPUs are connected to an existing Buck regulator rail of the IDTP9165, PFM mode operation is provided

by the power stage on board the IDTP9165, and occurs at light load after all DPU phases have been shed.

When the DPUs are used in conjunction with the IDTP9165 PMIC’s integrated controller, PFM mode operation is serviced by

the DPUs themselves. During PFM operation, the DPUs burst on and off concurrently at intervals controlled by the host

PMIC’s controller to maintain output voltage level.

THERMAL SHUTDOWN

Thermal shutdown occurs when die temperature exceeds 135°C. Once Thermal Shutdown occurs, the particular DPU will

permanently be disabled until the output voltage rail is power-cycled. Until then, the host PMIC’s integrated power stage and

remaining DPUs will have to absorb the extra load current. Thermal Shutdown on an individual DPU will not affect the output

voltage rail unless the host PMIC over-heats and shuts down as well, or if only one DPU is used in conjunction with the

PMIC’s integrated controller.