January 28, 2014

10

IDTP9167

Advanced Datasheet

APPLICATION

Typical Application Diagram

0.47µH

VCC

DCD1

VDDQ

V1.0A

VSYS_5V

IDTP9165

DCD0_LX

DCD0_FB

DCD1_LX

DCD1_FB

DCD0_VIN

DCD1_VIN

DCD2_LX

DCD2_FB

DCD3_LX

DCD3_FB

DCD2_VIN

DCD3_VIN

DCD0_GSEN

DCD1_GSEN

0.47µH

10µF

2x10µF

PVIN_12V

1µF

IDTP9167

LX

PGND

PVIN

VSYS

RSET

VPG

DIO

DIF

60.4kΩ

DCD1_DIO

DCD1_DIF

IDTP9167

LX

PGND

PVIN

VSYS

RSET

VPG

DIO

DIF

SoC

1µF

0.47µH

10µF

10µF*

4.7µF

4.7µF

53.6kΩ

2x10µF

6 x 47µF

PGND

Optional

*

*

*

Figure 5 – Typical application diagram showing two IDTP9167s connected as DPUs to augment the output current capability of

the IDTP9165 PMIC’s VNN rail.

In Figure 5, the 10µF capacitor placed next to the inductor of each DPU may be omitted if board space is limited, and the

main output capacitor cluster is within approximately 2 inches away. The inductance value of the LX inductor connected to the

DPUs may need to be 1µH in some applications as listed in Table 7. The RSET resistor value of each DPU is dependent on the

phase of the particular DPU, and whether the DPU is connected to a controller on the host PMIC, as shown in Table 8.