January 28, 2014

15

IDTP9167

Advanced Datasheet

PCB LAYOUT CONSIDERATIONS

DIO, DIF Communication lines

The DIO and DIF signals transition at a controlled edge rate of typically 8ns with a driving impedance of 70Ω. In most

applications, these lines do not need to be treated as transmissions lines, but it is recommended to use trace widths for Z0 of

around 70Ω for optimum signal integrity. In the case when DPUs are widely distributed (e.g. at the 4 corners of the load

device), avoid branching or using star-connection on DIO & DIF lines as this may cause signal degradation due to

unnecessary reflections at branch points.

COUT Placement

All COUT capacitors should be clustered together and placed as close to the load device as possible. The feedback voltage and

ground sense lines of the host PMIC should be connected across the load capacitor bank.

For optimum device performance, the following guidelines should be observed. Please contact IDT for Gerber files that

contain the recommended board layout.

•

The CVSYS & CVPG decoupling capacitors should be mounted on the component side of the board, close to their respective

pins. It is recommended not to use Vias between the decoupling capacitors and their pins and to keep their PCB traces as

short as possible. Due to the high switching currents possible and the high input voltage range, the CPVIN mounting

inductance should be less than the CPVIN capacitor’s ESL, which is around 1nH. This can be accomplished by placing

CPVIN as shown in the Recommended Board Layout, using only top layer route to connect to the PVIN and PGND pins,

minimizing inductance in the PVIN-PGND loop.

•

If the PVIN plane or the ground plane is not the top layer, then Vias can be used outside of the PVIN-PGND loop to

connect the IDPT9167 to those planes. For the PVIN connection, the average input current for typical operating

conditions is:

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Since the CPVIN capacitor case size can easily allow a 4-Via connection, this should be used. For the PGND connection,

the average input current for the typical conditions is:

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This requires more Vias. The number of Vias connecting the PGND and EPAD to the ground plane should be maximized

for thermal consideration. It is recommended that at least 10 Vias are used for this connection for typical application.

•

The DFN-12 package has an inner thermal pad which requires blind assembly. It is recommended that a more active flux

solder paste be used such as the Alpha OM-350 solder paste from Cookson Electronics (http://www.cooksonsemi.com).

Please contact IDT for Gerber files that contain recommended solder stencil design.

•

The package center exposed pad (EPAD) must be reliably soldered directly to the PCB. The center land pad on the PCB

(set 1:1 with EPAD) must also be tied to the board ground plane, primarily to maximize thermal performance in the

application. The ground connection is best achieved using a matrix of plated-through-hole (PTH) Vias embedded in the

PCB center land pad. The PTH Vias perform as thermal conduits to the ground plane (thermally, a heat spreader) as well

as to the solder side of the board. Recommendations for the Via finished hole-size and array pitch are 0.3mm to 0.33mm

and 1.3mm, respectively.